Test Scheme Drops FPGA Cost Below Structured ASICs

Nov. 29, 2004

ASICs have always put the price pressure on FPGAs. Traditionally, ASICs are more cost effective in large volumes. Over the last few years, though, the winds have begun to change. Xilinx hopes to continue this trend with its EasyPath series of Spartan-3 and Virtex-4 family FPGAs. Starting at just $12.95 per 30,000-logic-cell chip, these devices cost about half as much as comparable structured ASICs.

The silicon in the Spartan-3 and Virtex-4 FPGA families is the same as in the EasyPath devices. Yet Xilinx reduced testing costs by performing application-specific testing instead of generic FPGA testing. The company works with customers who already have a completed FPGA design. Such customers also have a "locked in" logic configuration and are looking to lower production cost. The EasyPath software analyzes the customer's configuration and maps the test requirements to the cells used, considerably shrinking test time and cost.

By more selectively testing the FPGAs, Xilinx also can recover FPGAs that might otherwise have been disqualified due to a bad logic cell or two. Such a goal is possible because those cells wouldn't be used in the application submitted by the customer. With fewer chips disqualified, the yield per wafer increases and the cost per chip decreases, further chopping the price for the customer.

Unlike ASIC approaches, EasyPath FPGAs possess a low nonrecurring-engineering (NRE) charge. They don't require any additional engineering or requalification costs, intellectual property, or tool investments either, since the chips are actually the same as the FPGAs used to develop the system. Designers can calculate their design-specific savings for EasyPath FPGAs using the free cost analyzer at www.xilinx.com/easypath/costanalyzer.

EasyPath solutions range in price from 30% to 80% below their standard FPGA counterparts. For example, in addition to the $12.95 list price for the Spartan-3 EasyPath E3S1500 (due in the second half of 2005), there's a $75,000 NRE cost and 50,000-unit minimum order.

Xilinx Inc.www.xilinx.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.