FPGA Advances Pave The Way Toward True SoC Solutions

Jan. 12, 2006
Move over, full-custom digital ASICs. Field-programmable gate arrays (FPGAs) are taking over many applications once considered the exclusive domain of those full-custom chips. FPGAs have usurped the ASICs by increasing gate counts by more than three orde

Move over, full-custom digital ASICs. Field-programmable gate arrays (FPGAs) are taking over many applications once considered the exclusive domain of those full-custom chips. FPGAs have usurped the ASICs by increasing gate counts by more than three orders of magnitude since their inception about two decades ago. Also, they've added high-speed I/Os, embedded memories, dedicated phase-locked loops (PLLs), and in a few cases, embedded processors. An important aspect of designing with FPGAs is the availability of pre-designed circuit blocks in the form of intellectual property (IP) that designers can license and integrate into their system. (For more about IP, see "IP Pulls It All Together" online at www. elecdesign.com, Drill Deeper 11841.)

Yet FPGAs haven't leapt into systems that require analog functions. Mixed-signal ASICs continue to rule this roost. That soon may change, though, with Actel's Fusion family of mixed-signal FPGAs (Fig. 1). These flash-based programmable system chips (PSCs) offer analog-to-digital converters (ADCs), analog inputs, MOSFET drivers, voltage references, and other analog functions, in addition to the programmable logic fabric and nonvolatile flash memory.

Other companies combine programmable analog functions with a small amount of programmable logic. Cypress Microsystems offers its pSOC programmable system-on-a-chip (SoC) family, and then there's Lattice Semiconductor's ispPAC Power Manager II family.

The Actel Fusion PSC gate capacities range from 90 kgates on the smallest device to 1.5 million gates on the largest device. The chips pack from 256 kbytes to 1 Mbyte of user-programmable flash storage, in addition to the flash-based fabric configuration memory. Furthermore, to ensure data integrity, the flash memory includes single-bit error correction and dual-bit error detection.

The integrated ADC can be configured for 8-, 10-, or 12-bit resolution, and the internal voltage reference provides a stable 2.56-V output. Up to 30 scalable analog input channels are available to serve as temperature, voltage, or current-sense inputs. Thanks to the high-voltage process needed by the flash memory, designers leveraged that technology to enable the prescalable analog inputs to handle high-voltage direct-connects of up to ±12 V.

With the converter and analog input pins, as well as 10 independent MOSFET gate driver outputs, the Fusion PSCs can perform many power-management and system-management tasks (e.g., fan control) that would otherwise require multiple external analog or mixed-signal circuits. The ADC, which can support up to 600 ksamples/s, features a differential nonlinearity of less than 1 LSB.

To control the converters and other system functions, soft CPUs such as an 8051 or ARM can be configured in the logic fabric. For power-sensitive applications, the PSCs offer ultra-low-power sleep and standby modes.

THE DIGITAL LEADING EDGE Today's digital FPGAs head in two major directions to better meet system demands: high-density, high-performance applications and moderate-density, cost-sensitive applications. At the high-capacity end, where top-notch performance is mandatory, SRAM-based FPGAs leverage 90-nm design rules to deliver capabilities comparable to many ASICs.

The largest devices in the Altera Stratix II family and the Xilinx Virtex II Pro and Virtex 4 families now pack close to 5 million gates and up to 9 Mbits of SRAM. Many of these chips also integrate I/O buffers or serializer/deserializer ports capable of multigigabit/s data-transfer rates, dedicated multiplier-accumulator (MAC) blocks, and multiple PLLs for clock distribution.

And it won't stop there. FPGA vendors are already at work on architectures that will be implemented on next-generation, 65-nm processes. Such designs probably will double the number of gates and pack even more embedded memory and dedicated DSP support, as well as still higher-speed I/O buffers.

To speed computations in DSP algorithms and other multiplication-intensive applications, many FPGAs now embed dedicated MAC blocks. These MAC blocks, in aggregate, can deliver hundreds of GMACs/s.

The largest Stratix II chip contains 384 dual 9- by 9-bit multipliers that each operate at up to 450 MHz (768 9-bit multipliers running at up to 450 MHz for a throughput of 346 GMACs). The multipliers also can be configured as 18- by 18-bit units for an aggregate throughput of 173 GMACs.

The Xilinx Virtex 4 SX55 FPGA, packing 512 dedicated 18-bit multipliers, can deliver an aggregate throughput of 256 GMACs when clocked at 500 MHz. Still higher performance will be possible when the next-generation, 65-nm designs are released.

The high-speed I/O buffers available on these high-performance FPGAs can handle the 3.125-Gbit/s data rates to implement current XAUI, SPI-4.2, and Fibre Channel interfaces. Even higher-speed I/O buffers, which come with Altera's Stratix IIGX series, offer data-transfer rates of up to 6 Gbits/s. Also, several members of the Xilinx Virtex 4 family pack 10-Gbit/s ports based on Xilinx's Rocket I/O technology.

Such high performance comes at a price, though. The largest devices in each company's families typically sell for as much as several thousand dollars each in moderate quantities. That price usually relegates the high-capacity chips to system prototyping, configurable compute accelerators, and ASIC emulation systems.

If the configuration pattern can be locked, converting the FPGA to an ASIC or structured ASIC might be an economically viable alternative. Altera offers its Hard-Copy structured ASIC option. Also, several ASIC vendors offer pin-compatible replacements for both Altera and Xilinx FPGAs.

Xilinx offers a different approach called EasyPath, which still uses FPGAs but implements a scheme that can leverage FPGAs that may have a few nonworking gates or I/Os. Software maps the logic to bypass the nonfunctional portion of the FPGA and thus allows the company to use chips that may otherwise have been discarded. The improved chip "yield" enables Xilinx to sell the chips at a significantly reduced price.

TACKLING VOLUME MARKETS Supporting more modest counts of up to about 1.5 million gates are FPGA families designed and priced for high-volume applications—consumer goods, flat-panel monitors, HDTVs, and many other systems with short market windows (Fig. 2). Examples include Xilinx's Spartan 3E series, Altera's Cyclone II family, Lattice Semiconductor's EC and ECP families, Actel's ProASIC 3 family, and QuickLogic's Eclipse II family. These budget-priced FPGAs will cost as little as $1.30 each in large volumes, with megagate-complexity chips dropping below $9 in the second half of this year.

More recently, several FPGA suppliers have focused on low standby power so the FPGAs can be used in portable systems. Take QuickLogic's recently released PolarPro family. In low-power standby mode, these devices draw as little as 10 µA—about one-tenth the power of other FPGAs with low standby currents. The active power also is modest, just 15 mA. Members of the PolarPro series offer complexities of up to about 1 Mgate and 202 kbits of RAM.

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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