FPGA Designers See Some Of EDA's Best Work In 2007

With so many designers making FPGAs their implementation vehicle of choice these days, it’s inevitable that some of EDA’s brightest minds would turn their attention to tools and methodologies targeted at getting the most out of these ever-more-capable devices.

One of the more interesting launches was from GateRocket, a startup that has seen FPGAs rise in size and complexity to ASIC-like levels. With that evolution comes a host of ASIC-like verification issues. For FPGA designers, just as for ASIC designers, simulation is too slow.

GateRocket’s RocketDrives are hardware units that take advantage of the actual target FPGAs to deliver simulation acceleration ranging from a factor of 10 to a factor of 100. The drives, which fit into a standard 5.25-in. PC form factor, are scalable to as many as eight units for system-level verification.

In a typical simulation flow, the device under test (DUT), testbench, IP, and custom logic are all run in the simulator itself. But with a RocketDrive flow, any or all of the parts of the FPGA design can be run in the RocketDrive on the native device (see the figure).

Sometimes, advances in FPGA tools come not from EDA vendors but from the FPGA makers themselves. Xilinx’s latest Integrated Software Environment provides runtime improvements for the company’s Virtex-5 silicon. Its “Smart- Compile technology” allows exact preservation of unchanged logic while revised logic is incrementally recompiled.

Mentor Graphics’ Precision RTL Plus jumps on the incremental bandwagon by offering two different incremental synthesis flows. One is fully automatic and requires no partitioning, while the other is partition-based for a divide-and-conquer approach. Mentor’s latest synthesis suite also provides an average FMAX gain of 10% for 19 different FPGA families from numerous vendors.

A final bright spot this year was vendors actually working together for the good of their common customers, something that happens all too infrequently. Cadence Design Systems and Mentor Graphics decided to cooperate in the spirit of the hype that accompanied SystemVerilog onto the scene by rolling out a joint Open Verification Methodology.

After all, SystemVerilog was promised as a hardware description language that would enable designers to build testbenches and capture them in verification IP (VIP) that could be reused time and again. Further, these verification testbenches and IP would be portable across platforms and distributed environments from various EDA vendors.

But the reality hasn’t matched the hype. SystemVerilog users found themselves cursing EDA vendors, whose verification methodologies haven’t delivered the kind of portability they promised. The Open Verification Methodology (OVM) addresses this with established interoperability mechanisms for VIP, transactionlevel, and RTL models, and full integration with other languages used in production flows. The OVM will also include a robust class library and be available in source-code format.

Yet even as EDA vendors work together here, they diverge elsewhere. For example, two distinct camps have formed over standards for representation of power-related design data. One camp, led by Magma Design Automation, Mentor Graphics, and Synopsys, promulgated the United Power Format that was formed in response to Cadence’s earlier Common Power Format (CPF) initiative.

In both cases, the idea is roughly the same: the formats comprise a mechanism through which a power architecture can be defined early in the design cycle and then carried through to implementation using a single view. Cadence responded with a complete low-power design, verification, and implementation flow that lets an engineering team, or groups of teams, leverage the CPF to capture lowpower design intent at the outset of the design process and then propagate it throughout the flow.