Low-Cost FPGAs Spin Out High Performance

July 19, 2004
Leveraging 90-nm process rules and a logic architecture that minimizes chip area, the Cyclone II FPGAs deliver a cost-sensitive, high-performance solution.

Diminishing lifetimes of consumer and other mass-market electronics have pushed system developers beyond just creating an ASIC to meet system needs. FPGAs tend to cost more than an ASIC at the component level when you consider development cost, nonrecurring engineering charges, shortened product life to recover development costs, and so forth. Yet they're an attractive alternative, even in high-volume applications.

Introductions like Altera's Cyclone II low-cost FPGAs further enhance this attraction. These FPGAs, developed for low-cost volume applications, cost $0.65 per 1000 logic elements (LEs). Initially, the family will include six members that range in logic capacity from 4608 to 68,416 LEs and from 119 kbits to 1.152 Mbits of on-chip SRAM (see the figure). Consequently, the smallest device, the EP2C5, costs under $3 in large volumes.

The on-chip SRAM is laid out in 4096-bit memory blocks (and an additional 512 parity bits). Each block can be configured in x1, 2, 4, 8, 9, 16, 18, 32, or 36 organizations. True dual-port operations (one read/one write, two read, or two write operations) are possible for all configurations except the x32 and x36 organizations.

The chips sport from 142 up to 622 I/O pads, some of which support low-voltage differential signaling (LVDS) at data rates of up to 805 Mbits/s (receiving) and 622 Mbits/s (transmitting). The I/O pads also support mini-LVDS, RSDS, LV PECL, differential HSTL, and differential SSTL. Single-ended interfaces include 2.5- and 1.8-V SSTL class I and II; 1.8- and 1.5-V HSTL class I and II; 3.3-V PCI and PCI-X 1.0; 3.3-, 2.5-, 1.8-, and 1.5-V LV CMOS; and 3.3-, 2.5-, and 1.8-V LVTTL. To handle external memory expansion, the FPGAs' dedicated memory interface supports DDR2 DRAMs and QDR II SRAMs. It operates at data rates that reach 333 Mbits/s.

The Cyclone II series includes phase-locked loops for clock distribution and timing control—two on the smallest family members and four on the larger devices. To support many signal-processing applications, the chips integrate dedicated 18-bit multiplier blocks. The small EP2C5 packs 13 multiplier blocks, while the largest family member, the EP2C70, delivers 150 such blocks. Also, the multipliers can be split into two independent 9- by 9-bit units to better work on byte-sized data such as video. The multipliers can operate at throughput rates of 250 MHz.

To improve logic efficiency, designers increased the size of the logic array blocks (LABs). In the previous Cyclone family, these blocks each contained 10 LEs. The new series packs 16 LEs in each LAB. This decreases the inter-LAB routing required because larger functions could now be implemented within a LAB. Even though the routing in each LAB increases, expanding the chip area, this is more than offset by reductions in inter-LAB routing. The reduced routing also helps improve performance and cut down on overall chip size.

The routing structure was modified to further shrink the chip and bolster performance. In addition to the horizontal and vertical routing paths that spanned four LABs in the Cyclone I series, the Cyclone II devices added even longer routing segments to reduce signal delays for long routes.

In addition to all of the hardware resources, the Cyclone II FPGAs can readily accommodate soft cores like the Nios II CPU core. For example, implementing a 100-MIPS version of the CPU core on the EP2C20 requires only 546 of the over 18,000 LEs. Many other cores, such as 10/100 Ethernet MACs, PCI and PCI-X interfaces, FFT and FIR compilers, and SPI-4.2 interfaces, are available either in the company's library or through third-party suppliers. Free development tools can be downloaded from the company's Web site.

Altera Corp.www.altera.com


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