VHDL Package Targets 100K+ Gate FPGA Designs

Targeting 100,000-plus gate FPGA designs, Active-VHDL 3.2 is an integrated, Windows NT/95-based, VHDL design entry and verification environment for mainstream FPGA/CPLD designers. In the new version, the interpretive VHDL simulation kernel has been replaced with direct compile technology, providing an enhanced platform for high-density device verification. The simulation kernel compiles VHDL code directly into Pentium-optimized machine code, resulting in what's claimed as significant performance and memory allocation improvements.