FPGA Design Suite Generates Global Minimum Layout

April 26, 2012
Users of Xilinx’s Series 7 FPGAs will have a choice between two development tools. The Vivado Design Suite supports all of the Series 7 FPGAs and will be the development tool for all future FPGAs from Xilinx

Users of Xilinx’s Series 7 FPGAs will have a choice between two development tools. Now in its 13th revision, Xilinx’s ISE supports all of the company’s FPGAs. The Vivado Design Suite supports all of the Series 7 FPGAs and will be the development tool for all future FPGAs from Xilinx. The company does have an upward migration path, with Vivado able to load ISE projects. Existing projects are likely to remain on ISE, but new projects may take advantage of Vivado and its improved capabilities.

Figure 1. Layout on the 1.2M logic cell Virtex-7 2000T FPGA can be challenging. The left side was completed using ISE, requiring 13 hours and 16 Gbytes of memory, while the right side was finished using Vivado running for only five hours and using only 9 Gbytes.

Xilinx’s multi-slice 1.2M logic cell Virtex-7 2000T FPGA (see “10,000 Connections Between FPGA Slices” at electronicdesign.com) highlights one of Vivado’s advantages and its improved place-and-route technology (Fig. 1). The faster tool uses less memory to calculate the best layout by finding the global minimum using an analytical solver rather than searching for local minimums like ISE or performing place-and-route like most other systems (Fig. 2).

Figure 2. Vivado's place-and-route finds the global minimum for an FPGA layout.

Vivado solves N equations with M unknowns plus cost function that can address timing, wire length, and congestion. The deterministic place-and-route also provides automatic clock gating support. Typically, there’s a 30% reduction in power with only a 1% increase in logic. This optimization support can be managed by component intellectual property (IP) or within the design hierarchy.

Xilinx could have stayed with ISE if it was simply a matter of improving the place-and-route compiler. Vivado, though, incorporates significant changes in the way designers approach the FPGA design problem and implement designs. That’s why Vivado was designed from the ground up with a significant emphasis on IP integration. It utilizes a hierarchical chip planning and design approach and supports multi-domain and multi-die (like the Virtex-7 2000T) physical optimizations. The design hierarchy impacts everything from place-and-route to power management.

IP integration uses a drag-and-drop interface with designers choosing items from the catalog. Items designed to provide AMBA AXI4 (Advanced eXtensible Interface 4) support can be automatically connected using drag-and-link operations. ARM developed the AMBA AXI4 interconnect protocol, and a range of ARM hard and soft-core processors supports it. Not surprisingly, Xilinx’s Zynq-7000 EPP (Extensible Processing Platform) incorporates dual ARM Cortex-A9 cores with AXI4 support (see “FPGA Packs In Dual Cortex-A9 Micro” at electronicdesign.com).

ISE provided AXI4 support, but Vivado significantly extends these features. The idea is to deliver a design that is correct by construction. This does not eliminate the need for detailed logic design since the tool can be used for this as well. Likewise, Vivado includes a packaging tool to enable items to be created and added to the catalog.

Large systems can be built quickly from components, but they take longer to compile. Incremental compilation can significantly reduce this time. Vivado’s incremental nature addresses engineering change orders (ECOs) and the effect of rippling changes as a design changes over the life of a project. It incorporates its own ECO database.

Components can be configurable, and designers can experiment with various constraints without changing the underlying system. Designers then can examine alternatives quickly, especially with incremental compilation. Also, Vivado’s simulation support is three times faster than ISE. It supports hardware co-simulation that can improve simulation times by a factor of 100 as well.

The Vivado integrated development environment (IDE) is based on JIDE (Fig. 3). It also incorporates the Tool Command Language (Tcl) for advanced scripting. Tcl is commonly used in embedded applications for rapid prototyping. Xilinx’s software development kit (SDK) is still based on the Eclipse IDE and works with hard-core and soft-core designs created using Vivado.

Figure 3. Vivado's IDE is based on JIDE.

The tool comes in three versions. The free WebPACK includes the software SDK. It has limited simulation support. The Design Edition has a complete simulation and debugging package including a logic analyzer and high-speed serial I/O analysis. The high-end System Edition adds high-level synthesis and DSP generation.

Vivado is a major change for Xilinx, and it throws down the gauntlet to the competition. It offers enough enhancements to conventional FPGA developers, but the incremental, hierarchical design approach and AXI4 linkage open the doors to many other users. ISE will remain so migration isn’t immediately mandatory, but it is the wave of the future for Xilinx and its customers.

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