128 Mb Flash Uses Multi-Bit Cell Technology

March 1, 2003
Employing multi-bit cell technology based on the company's 0.15 µm process, a family of 128 Mb flash memories store two bits of data per cell to reduce the area of the memory array by as much as 50% compared to single-bit cell technology. Two

Employing multi-bit cell technology based on the company's 0.15 µm process, a family of 128 Mb flash memories store two bits of data per cell to reduce the area of the memory array by as much as 50% compared to single-bit cell technology. Two versions of the memory include the M58LW128A with a 16-bit-wide data bus and the M58LW128B that can be configured with a 16- or 32-bit wide data bus. Both are organized as 128 blocks of 1 Mb, allowing one device to store code and data. Each block has its own security mechanism that can be used to protect boot code or data. Both devices operate from a single supply, and program, erase, and read operations are executed via a 2.7V to 3.6V supply. Programming can be done in-system on a 16 word or eight double-word basis and can be electrically erased at block level. Other features include 100,000 program/erase cycles per block and a 20-year data retention. The M58LW128A is available in a 56-lead TSOP and a 64-ball TGBA. The M58LW128B is available in an 80-ball TBGA. Pricing for the M58LW128 is $10 each/500,000. STMICROELECTRONICS INC., Lexington, MA. (781) 861-2650.

Company: STMICROELECTRONICS INC.

Product URL: Click here for more information

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!

Sponsored