Multi-Time Nonvolatile Programmable Memory Supports 40nm

April 29, 2011
Kilopass' Itera technology can be incorporated into 40nm designs. The multi-time nonvolatile programmable memory technology has a 20ns access time.

Itera comparison of features

Itera technology block diagram

Kilopass has been known for its one-time programmable memory (OTP) technology. The new Itera technology (Fig. 1) delivers multi-time programmable support and delivers this for 40nm environments. It can provide native programmability with 20nm access times versus technologies like flash that currently scale to 90nm. Its endurance is lower, up to 1K cycles, but this is often more than sufficient for many applications. It does not require additional wafer fab steps making it suitable for a wide variety of devices. It can be used for storage requirements up to 1 Mbit at this point (Fig. 2).

Itera can address OTP applications such as security and configuration information. It can also handle applications that OTP is not suitable for such as program and boot code that has the potential to change slowly over time. These kinds of applications are ideal for Itera especially where a small footprint is needed using the latest 40nm technology. Itera scales at least to 28nm making it compatible with the latest high performance processors and FPGAs.

One place that the new technology would be great for is the boot code for high performance microprocessors. Currently this approach often employs a very basic, two stage boot system using serial memories that are inexpensive and easy to interface. The main boot program is contained in these devices that in turn load more complex boot programs from other devices such as hard drives or network storage. Itera could eliminate the external memory while providing the same level of customization but with even better performance. In fact, it could address features that are often place in ROM.

Itera's sweet spot would be on-chip but it could find its way into off-chip memory. Even a serial device would be a candidate providing higher throughput. Cost savings will vary depending upon where the memory is located but there should be savings regardless of where it is employed.

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William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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