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Non-Volatile NRAM Nanotubes Deliver Endurance and Performance

June 3, 2015
Nantero’s non-volatile, nanotube-based NRAM is the latest memory technology to try to unseat DRAM and flash memory.

Nantero’s nanotube-based NRAM technology has an impressive feature list. It has the read/write speed of DRAM with flash memory’s non-volatility but with significantly higher endurance. It can retain data for more than 1,000 years at normal temperatures. It is also amenable to the latest CMOS technology scaling below 5 nm as well as supporting MLC (multi-level cell) and 3D structures. Best of all it works with current CMOS fab technology.

NRAM is based on film of crossed nanotube (CNT) deposited on a silicon substrate. Each cell can be switched between a low and high resistive state (Fig. 1) that is stable in excess of 300° C.

1. The crossed nanotube (CNT) fabric can be changed between high and low resistive states.

The CNT layer is etched using standard lithography techniques. A single cell has hundreds of nanotubes (Fig. 2). They are scattered, but proper alignment is required for it to act as a programmable storage device. Changing the cell’s state requires application of a programming voltage for a few picoseconds. Experimental chips have reached 1012 write cycles and 1015 read cycles.

2. A typical NRAM cell has hundreds of nanotubes.

NRAM addresses almost all aspects of storage, given its potential scalability and performance. It is especially well suited for embedded applications because it is compatible with conventional CMOS technology, allowing it to be employed in microcontrollers. Its wide operational temperature range will allow its use in rugged applications like automotive and aviation.

NRAM—like previous technologies such as FRAM, MRAM, and phase-change memory—has the potential to unseat the existing DRAM/flash combination that currently dominates computer technology. It remains to be seen whether it will be a winner or a niche player, but it is looking good so far. Nantero is currently licensing its technology. Initial chips are expected to be compatible with DDR4 interfaces. 

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

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