Visual Signal Processor Excels At Imaging And Video Apps

Claimed as an industry first, the CW4011 visual signal processor (ViSP) is the first member of a highly scalable, embedded processor family representing a new approach to image and video processing. It is built on a 32-bit fixed-point processor core comprised of a single instruction multiple data (SIMD)/Vector DSP and a RISC microprocessor. It has traditional vector features, as well as enhanced vector processing with features such as end-of-array handling, run-time variable numbers of datapaths, table operations, and unlimited conditional nesting. It supports a 16/32-bit SDRAM interface and a 16-bit host/peripheral interface. It also includes separate 16-bit video-in and video-out ports that support simultaneous data transfers at a 100-MB/s rate. A 3-channel DMA controller, 3-wire SPI serial interface, UART, JTAG/SCAN unit, 16 GPIO, and 3 timers round out the I/O and support functions. The CW4011 ViSP will support applications ranging from very cost-sensitive products such as digital cameras to very high-performance products such as video transcoders. At over 4,000 MIPS, it is reportedly twice as fast as similar solutions based on general-purpose DSP architectures. And at 0.10 mW/MIPS, it supports the low power requirements for the next generation of battery-powered devices. The CW4011 is available with a full software development kit that includes an optimizing C compiler, a cycle accurate software simulator, a visual (JTAG) debugger and assembler, and a performance profiler--all based on the Metrowerks CodeWarrior IDE. The development software supports both Microsoft Windows and Linux-based platforms. Samples of the CW4011 ViSP running at 200, 233 and 266 MHz are available today; production volumes will be available in Q3 2002. The 208-pin device is available in a PQFP or BGA package, with pricing for the 200-MHz part pegged at less than $20 each/10K. CHIPWRIGHTS, Newton, MA. (617) 928-0100.