ASICs Stumble At 45 nm

Jan. 15, 2009
The steady progress of ASIC design in embracing each new semiconductor process node has stalled at 45 nm. Meanwhile, earlier process generations remain viable as mask costs fall.

The steady progress of ASIC design in embracing each new semiconductor process node has stalled at 45 nm, and it may take some time to jump through that hoop. Growing design challenges, rising costs, and shrinking benefits face users of the latest processes, with relief far from sight. So instead of designs moving in a wave toward new generations, the adoption curve is flattening out. Therefore, many process nodes remain viable even though they’re many generations old.

At first glance, it would seem that the decade will end as it began for ASICs, with designers steadily migrating their projects through the generations of process nodes as fast as they arise. This steady migration even had a structure. Early adopters rushed to embrace the newest process node. Mainstream designs representing the bulk of the market shifted to the former leading edge. And, laggards followed another generation or two behind.

In the past, this adoption wave moved steadily along, keeping pace with process technology development. But the leading-edge adopters have hit a snag, and the rest of the pack is spread out over five prior generations.

Semiconductor foundries are doing their part to keep the pace steady. China’s Semiconductor Manufacturing International Corporation (SMIC), for example, announced its first 45-nm yield lot in late 2008, signifying a working process that will deliver production volumes to design customers in 2009.

Similarly, in late 2008, TSMC achieved volume production of both its low-power and general-purpose 40-nm processes, and UMC validated its 45-nm process with a successful SRAM product yield. Further, UMC indicated that it’s making steady progress toward having its 32/28-nm technology available in 2010.

Adoption of these evolving technologies isn’t keeping pace as it once did, though. According to Colin Baldwin, director of marketing at ASIC design house Open Silicon, the adoption curve is flattening. Baldwin reported requests for quotes (RFQs) in hand for 40-nm designs for the past year, numerous designs in process for 65-nm and 90-nm technologies and designs at 130 nm still closing. Further, Baldwin noted, the optimum cost point for designs requiring embedded flash memory lies with 180-nm process technology.

Financial reports from semiconductor foundries provide supporting evidence. According to the Q3 2008 figures from UMC, sales are fairly evenly split across multiple process generations (Fig. 1). Even as 45-nm technology gears up to production, process technologies as many as seven generations removed still show substantial strength.

COST PATTERNS SLOW PROCESS ADOPTION • A variety of factors contributes to the slowdown in new technology adoption for ASIC designs. One is the rising cost of production masks for leading-edge technologies. A mask set for 40-nm production has a nearly $2 million price tag. At the same time, production costs for the older technologies are dropping rapidly.

Baldwin noted that mask sets for 65-nm designs have dropped below $1 million and that 10-Mgate designs at 130 nm can be brought to production for $400,000, including all design engineering, test, and validation efforts and foundry nonrecurring-engineering (NRE) charges. Such upfront cost differentials have made the adoption of a newer technology a harder sell to management.

The struggling world economy may further compound the cost differentials as foundries juggle pricing to fill capacity and remain profitable. UMC, for instance, reported in late 2008 that its annual sales dropped more than 10% from the prior year and its production lines were less than 80% full.

Another factor that’s slowing ASIC adoption of new processes is the burgeoning need to account for variability in manufacturing results. Dimensions of semiconductor features have become small enough whereby normal statistical variations in dopant distribution and other processes can result in significant circuit performance differences.

Studies from Intel show that deep-submicron devices can vary in performance by 30% and in critical parameters such as leakage current by 2000%. Models developed at STMicroelectronics support that finding, showing substantial variation in the ON and OFF currents for transistors fabricated at 65 nm (Fig. 2).

A third factor impeding process migration is a decline in benefits. According to Intel researcher Shekhar Borkar, the historical gains in performance and power obtained through process shrinks are diminishing. Borkar noted that historically as transistor integration doubled according to Moore’s Law, the gate delays reduced 30%, energy use per logic operation declined 65%, and overall power consumption declined 50%.

But the supply voltage and threshold scaling that provided some of these benefits will slow or stop in the emerging generations. Thus, transistor density will continue increasing while other improvements slacken. Combined with the rising NRE costs, the reduced benefits make migration less attractive.

Then there’s the question of design difficulty. The availability of third-party silicon intellectual property (IP) in the form of fully developed subsystem blocks was supposed to simplify the design of multimillion-transistor chips. But as transistor counts rise, the complexity of the available IP remains essentially stable. The main focus of new IP development recently, for instance, has concentrated on high-speed serial communications and small video processing blocks. Renesas recently announced IP for a PCI Express 2.0 interface that can operate at 5 Gbits/s. Also, eASIC made available for its customers’ video building blocks such as downscalers and color space converters from IP vendor Video-Cores.

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While the availability of such IP frees ASIC designers from some detail work, individual cores don’t represent a major fraction of the total design. That fraction declines as designs grow to fill the space available with new process generations. Consequently, the design task gets more difficult with each process generation.

ESL METHODOLOGIES ON THE FAR HORIZON • In light of those reports, there’s still some cause for optimism. Tool vendors increasingly look to electronic-system-level (ESL) design to simplify the creation of ASICs that can fully utilize the transistor counts available from emerging process generations. The ESL approach would allow ASIC developers to create their designs at a higher level than stitching together IP blocks.

According to Frank Schirrmeister, director of product management at Synopsys, several essential requirements for an industry-wide shift to ESL methodologies are already in place. Schirrmeister pointed out, for example, that the use of SystemC to describe chip designs at a transaction level is already occurring, although it’s primarily used today by software developers as a validation target.

A new SystemC TLM2 specification helps standardize transaction abstractions to support the interoperability of tools using SystemC. Schirrmeister also noted, though, that other capabilities still need to be in place before hardware design can switch over, including register-transfer-level (RTL) synthesis tools utilizing a subset of SystemC and tools for equivalence checking between SystemC and RTL designs. Such tools are under active development or in their first commercial incarnations, says Schirrmeister, so the shift to ESL methodology seems inevitable.

Another hope comes from a shift in what ASIC developers seek to gain as they migrate to new processes. According to Open Silicon’s Baldwin, designers today are less interested in ever-increasing performance and more interested in adequate performance at an optimum power point.

This shift, Baldwin explains, parallels the change in the computing industry where faster clocks have given way to increased parallelism. As this paradigm shift takes hold in the market, the slowdown in performance gains of new processes becomes a moot point.

The shift in interest away from absolute performance additionally helps ASIC designers by opening an opportunity to handle process variability. This variability makes some chips faster with higher leakage and other chips slower with lower leakage. Normally, sorting would reject a substantial number of chips for inadequate performance or excessive power. If top performance isn’t required, however, such chips can be salvaged rather than scrapped.

The trick is to apply a bi-directional adaptive body bias (ABB) to the chip. The transistors in a CMOS ASIC are four-terminal devices: drain, source, gate, and body (Fig. 3). Typically, the body connection ties to ground. But researchers at Intel discovered that biasing this connection can shift the performance of a device either way depending on bias polarity.

Slow devices can run faster (with greater leakage), and fast devices can slow down and reduce leakage. This ability to shift performance on a chipby- chip basis can help counter process variability and increase yields in designs targeting the middle of the range.

For the remainder of the decade, then, ASIC designers can expect the trends of continual new process adoption and ever-increasing performance to falter. In their place will be more opportunities to choose a process point based on adequate performance, optimized power, and minimal cost. The trends will return in a few more years as design techniques shift to ESL approaches and techniques such as ABB arise to address the increasing process variability.

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