RISC ICs Meld Performance Of 16-Bit µCs And DSPs

June 1, 2001

The launch of a new architecture that melds circuitry for a high-performance 16-bit microcontroller with that for a moderate-performance digital signal processor promises to make motor control, Internet-connected appliance, automotive, speech recognition, and a host of other products easier and less costly to design, as well as make them run more efficiently. Based on a non-pipelined, modified Harvard RISC machine core, the 16-bit dsPIC architecture digital signal controllers can operate from a 2.5V to 5.5V supply and support up to 4 MB x 24 of addressable flash program memory and up to 32K x 16 of data space. And the dsPIC instruction set architecture is designed to be highly efficient for C compilers and RTOSs.
The new digital signal controllers boast of a slew of features, a few of which include up to 30-MIPS operation, two 40-bit wide accumulators with optional saturation logic, high current sink/source I/O pins, multiple external interrupt pins, a timer module, A/D converters, a watchdog timer with its own on-chip RC oscillator, and selectable power management modes. The several families of dsPIC devices under development are expected to have from 28 to 100 pins and cost $3 to $9 each/10,000. Beta sampling of the first devices is planned for Q4.


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