RISC/DSP Core Provides Platform High Volume ASIC Projects

Royalty free and capable of being implemented in as few as 20,000 gates, the company has paired its XPA2 16-bit RISC core with the APE2 DSP coprocessor to provide a time saving solution for ASIC and SoC applications involving data-intensive processes. The XAP2's architecture is optimized for low power consumption via extensive use of single cycle instructions, with an instruction set chosen for power efficiency and a sleep mode that uses virtually zero power. The DSP core allows users to configure and customize the core's very long instruction word (VLIW) processing architecture with dynamic data-path routing. Also provided free of charge, the company's 16-bit interface logic configures the DSP to act as a coprocessor to the host RISC processor. A shared RAM interface and dedicated control lines allow communication between the APE2 and XAP2. Both processors can operate simultaneously, with the XAP2 receiving notification when the APE2 has finished a task. DSP code can be fixed in ROM or downloaded into RAM by the host. For further information, contact Patrick Pordage at CAMBRIDGE CONSULTANTS LTD., Cambridge, UK. +44 (0)1223 420024.