Mixed-Language Simulator Serves FPGA Designers

In the Active-HDL Designer Edition, a low-cost mixed-language RTL simulator, designers gain a high-performance simulator for designs targeted at FPGAs. Basically, FPGA designers have been forced to choose between commercial FPGA simulators starting at $6000 or more and the restricted, single-language simulators supplied by their FPGA vendor for $1000 or less. The Active-HDL Designer Edition simulator fills that gap; it’s a mixed-language tool that costs less than $2000. Yet, it provides IEEE mixed-language simulation support for VHDL, Verilog and SystemVerilog. It’s said to run at least twice as fast as FPGA vendor-supplied RTL simulators. It also supports encrypted IP and imposes no limitations on FPGA design sizes. The tool gives users technical support directly from Aldec; software revisions and library maintenance are the same across all configurations of Active-HDL, providing a smooth upgrade path if additional functionality is required. Capabilities such as code coverage, design-rule checking, DSP modeling and verification, SystemC co-simulation, transaction level modeling or assertion based verification are available. Active-HDL Designer Edition is available now and supports Windows 32/XP/Vista operating systems. The product is offered as a one-year time-based license that is either node-locked ($1995) or floating ($2495). ALDEC INC., Henderson, NV. (702) 990-4400.