Digital ICs/DSP: Get 1 MFLOPS/MHz With Floating-Point Extensions To ARC CPUs

June 23, 2005

Floating-point extensions to the ARC600 and 700 32-bit soft processor cores enable the cores to deliver full-performance math functionality without a coprocessor. The logic extensions to handle the math implement the IEEE-754-compliant floating-point functionality with a significantly lower gate count than competitive floating-point coprocessors while delivering comparable performance. Floating-point throughput is typically about 1 MFLOPS/MHz, and both single- or double-precision implementations are available. The system designer also can add custom math instructions by using the company's extensible instruction-set architecture and development tools. Single-precision extensions are available now. The double-precision extensions will be ready by early in the third quarter. Contact the company for licensing details.

ARC International plc.www.arc.com/fpx

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.