Two-Million-Gate FPGA Targets Gigabit Applications

With twice the system-gate density and 50% better I/O performance compared with the original Virtex FPGAs, the firm's Virtex-E FPGAs are said to be capable of performance and density attributes that were previously in the ASIC domain. The FPGAs are suited for next-generation data communication and DSP applications. Among the devices' features are two-million-gate density, 640 kb of true dual-port internal block RAM, eight digital delay locked loops capable of clock frequencies of more than 300 MHz for system timing, and three new differential signal standards. The Virtex FPGAs are claimed as the first programmable devices to support direct interface to multiple differential signal standards, including LVPECL, LVDS and Bus LVDS. They carry up to 340 differential pairs capable of over 311 Mb/s per I/O pair for aggregate I/O bandwidth of over 100 Gb/s.