Merging 16- and 32-Bit DSPs with MCUs

Dec. 9, 2002

Merge a 32-bit DSP and a 16-bit microcontroller (MCU) into a single integrated unit and you've got one of Motorola's latest developments, the 56F800 architecture.

William G. Wong

Flash DSP/MCU Ropes In C/C++

Merge a 32-bit DSP and a 16-bit microcontroller (MCU) into a single integrated unit and you've got one of Motorola's latest developments, the 56F800 architecture. Fast interrupt support allows the chip to handle signal-processing tasks with features like single-cycle instructions, and no overhead hardware looping functions can take advantage of bit manipulation and other capabilities. A memory-based stack and large register file mean that it's suitable as a C or C++ target platform.

One version of this chip, the new 60-MIPS 56F83x, runs at 60 MHz with a standard operating temperature range of -40°C to 125°C. Peripherals include analog-to-digital converter (ADC) and pulse-width modules, quad timers, quadrature decoders, and a 2.0B FlexCAN module. Flash memory size ranges from 12 to 256 kbytes. A security feature prevents code access and corruption. Additionally, a 256-word page size allows EEPROM emulation.

Pricing for the 56F800 will start at $5.22 in OEM quantities.

16-Bit DSP Architecture Boosts MCU

Set up for C, Microchip's 30-MIPS dsPIC30F family homes in on the 16-bit DSP space with a microcontroller's peripheral complement. The 16-register-bank architecture is a significant advance over the company's 8-bit PIC microcontrollers (MCUs), but the dsPIC30F retains MCU features like a programmable brown-out reset and a low-voltage detect interrupt.

The data converter interface supports common codec protocols such as I2S and AC'97. A 10-bit analog-to-digital converter (ADC) handles up to 16 channels with two or four simultaneous samples. Communication support includes addressable UARTs for controller-area networks (CANs). Moreover, an I2C module features a multi-master mode and 7- and 10-bit addressing.

When it comes to memory, the dsPIC30F is flexible. A three-address generation unit handles dual data fetch and writeback for DSP operations. Up to 4 kbytes of EEPROM, 8 kbytes of SRAM, and 144 kbytes of flash memory are included. The address space for programs is 4 Mwords and data is 64 kbytes.

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.

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