Higher-Bandwidth DSP Covers Asia's Telecom Market

Nov. 1, 2004
This 850-MHz, DSP Base-Station Processor Boasts Lower Power And Wider Coverage For 3G Wireless-Networking Standards Like TD-SCDMA, GSM/EDGE, And cdma2000.

Few places have experienced the explosive wireless-telecommunication-network growth that has been seen in Asia. The demand for wireless devices and, more importantly, the networks that support them has been especially great in China. For instance, the Chinese Ministry of Information Industry (MII) recently estimated that the number of mobile-phone users in China has passed 315 million. As the demand for modern wireless networks grows, so does the need for base-station data-processing systems that enable greater bandwidth with more efficient power consumption. This need is felt keenly in China, where 3G wireless networks like TD-SCDMA are a booming business. TD-SCDMA is a network technology that has been approved by the International Telecommunication Union (ITU) for 3G standards. Several TD-SCDMA systems are now operating in trial setups in China.

Recognizing the need for data-processing devices that provide improved performance, TI has introduced the TMS320TCI100Q. By supporting greater bandwidth, this 850-MHz DSP device will help wireless service providers achieve wider network-coverage areas and clearer signals. The improved bandwidth of this device also will enable characteristic 3G features like wireless video download and real-time video conferencing over a cellular handset.

Usually, higher-bandwidth devices are associated with increased overall power consumption. This is not the case with the TCI100Q, claims Texas Instruments. For TD-SCDMA baseband processing, the company says that this DSP can reduce the number of processors for a full carrier system from three to two. This reduction in processor chips should lead to an overall power reduction of 20% per channel. Additionally, the device operates on a low 2 W of power.

Why are 3G network carriers so interested in a DSP that supports significantly higher bandwidth and lower effective power usage? More than half of the cost of such a network is found in the radio network subsystem (RNS), which is analogous to the base-station system (BSS) of a typical 2G network. Over half of the cost of that RNS is in the radio access network, which is commonly known as Node B.

Node B is the physical unit for RF reception and transmission within a base-station cell. It contains both analog RF and digital-baseband components. Perhaps the most critical element of the Node B datapath is the channel card. Existing 3G channel cards rely on a combination of DSP + ASIC architectures. These cards are a key factor in the base station's overall performance and cost.

By focusing on the development of more efficient DSPs, TI can help carriers realize significant cost and performance benefits in the design of 3G base-station channel cards. In terms of overall power, the cost of Node B's digital side can be scaled down much faster than the analog portion. For this reason, the TCI100Q DSP provides very effective overall power consumption.

For TD-SCDMA baseband processing, the TCI100Q device can reduce the number of processors for a full carrier from three to two. This chip reduction brings significant benefit to China's 3G TD-SCDMA carriers. But these same benefits extend to all major carrier standards, such as GSM/EDGE, UMTS, and cdma2000 transceiving applications. It also is a fit for transcoding/media-gateway designs.

By optimizing the architecture for base-station designs, the TCI100Q is able to meet the higher processing demands of 3G network standards while reducing the overall parts count. TI has been working closely with its customers to perform detailed benchmarking and dimensioning analysis. The company claims that these studies demonstrate that a single carrier of TD-SCDMA can fit on two TCI100Q DSPs at 850 MHz (FIG. 1). This is a substantial reduction from earlier prototype systems, which may have required six or more DSPs. The results are even an improvement over previous estimates, which concluded that three DSPs running at 720 MHz would accomplish the same processing performance.

The reduction of the number of DSPs is impressive. Yet the TCI100Q doesn't stop there. It also reduces the complexity of the interface between the DSPs and their associated power supplies. Thanks to the higher performance of the TCI100Q chip, this simplification results in system-level cost savings.

The TCI100Q is the newest member of the TMS320C64x family of fixed-point DSPs. It can perform up to 6800 million instructions per second (MIPS) at a clock rate of 850 MHz. The C64x family is scalable to higher clock speeds. To address a wide range of high-performance applications, it can incorporate multiple memory, peripheral, and voltage combinations.

The chip is based on Texas Instruments' next-generation very-long-instruction-word (VLIW) architecture, which is called the VelociTI.2. Because of its addition of Viterbi and Turbo co-processors, the TCI100Q also boasts higher system integration. The TMS320C64x is a code-compatible member of the larger C6000 DSP platform.

One of the features that makes the TCI100Q so attractive to base-station designers is its combination of operational flexibility and numerical capabilities. Such operational flexibility is usually found in high-speed controllers. Numerical capabilities are typically a part of array processors.

The chip's core processor supports 64 general-purpose registers of 32-b word length. In addition, it supports eight independent functional units. These units consist of two multipliers for a 32-b result and six arithmetic logic units (ALUs) with VelociTI.2 extensions. The extensions include support for packed data processing and special-purpose instructions to accelerate broadband-infrastructure and imaging applications.

The VelociTI.2 extensions in the eight functional units include new instructions to accelerate certain critical applications. Those instructions also extend the parallelism of the VelociTI architecture. The C64x can produce four 32-b multiply-accumulates (MACs) per cycle for a total of 3400 million MACs (MMACs) per second. Or it can produce eight 8-b MACs per cycle (for a total of 6800 MMACS). The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals that are similar to the other C6000 DSP platform devices.

In addition to the VelociTI extensions, the TCI100Q device has two high-performance embedded coprocessors: a Viterbi Decoder Coprocessor (VCP) and a Turbo Decoder Coprocessor (TCP). These devices significantly speed up channel-decoding operations on chip while freeing the MPU core to perform other operations. The Turbo coprocessor performs convolutional encoding for the symbol-rate processing used in 3G. Meanwhile, the Viterbi coprocessor handles 3G error correction. Together with the other TCI100Q components, these coprocessors can speed up the execution of common 3G algorithms that support voice and data coding (FIG. 2).

When operating at CPU clock divided by 4, the VCP can decode over 708 7.95-kbps adaptive-multi-rate (AMR) voice channels. The TCP—operating at CPU clock divided by 2—can decode up to 42 384-kbps or eight 2-Mbps turbo-encoded channels (assuming six iterations). The TCP implements the max*log-map algorithm. It is designed to support all of the polynomials and rates that are required by Third-Generation Partnership Projects (3GPP and 3GPP2) with a fully programmable frame length and turbo interleaver. Decoding parameters, such as the number of iterations and stopping criteria, also are programmable. Communications between the VCP/TCP and the CPU are carried out through the enhanced-DMA controller.

The TCI100Q DSP uses a two-level, cache-based architecture. It flaunts a powerful, diverse set of peripherals including a Peripheral Component Interconnect (PCI), a general-purpose input/output port (GPIO) with 16 GPIO pins, and two glueless external memory interfaces (64-b EMIFA and 16-b EMIFB)—both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

On the development side, the DSP chip has a complete set of tools. This toolset includes an advanced C compiler with TCI100Q-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source-code execution.

The TMS320TCI100Q was released to production on Sept. 30. Samples and production quantities are available now.

Texas Instruments, Inc. 12500 TI Blvd., Dallas, TX 75243-4136; (800) 336-5236, www.ti.com.


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