Dataplane Processing Unit More Flexible Than DSP

Sept. 10, 2009

Baseband communications dataplane processing is one of the most demanding environments around. Tensilica’s ConnX Baseband Engine is designed to address this challenge (see the figure). Tensilica calls its architecture a dataplane processing

William G. Wong

Baseband communications dataplane processing is one of the most demanding environments around. Tensilica’s ConnX Baseband Engine is designed to address this challenge (see the figure). Tensilica calls its architecture a dataplane processing unit (DPU), in contrast with CPUs and DSPs.

The processor cores are based on Tensilica’s Extensa LX. The system includes one scalar core plus eight SIMD cores. Verylong- instruction-word (VLIW) instructions control the scalar core plus an eight-way dual ALU engine and SIMD engine. The system is fed by 160-bit registers and a pair of 128-bit memory interfaces. It can mange up to eight vector divides and two square roots or four complex FIR taps or radix-2 and radix-4 butterfly operations/cycle. Also, it can perform 16 18-bit MAC operations/cycle.

Tensilica delivers custom configurations, so the base system is just the starting point. Options include multiple queue ports and 160-bit FIFOs via the SIMD vector registers. The processor interface can be linked to an AMBA bus, providing access to a wide range of peripheral IP. Connections can use a crossbar switch or bus. It can support multiple memory interfaces as well.

TENSILICAwww.tensilica.com

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.

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