Design Automation Addresses SoC Challenges Head On

Shrinking silicon geometries are challenging complex systems-on-a-chip (SoC) designers in two distinct ways. First, at 0.18 µm and below, it's becoming increasingly difficult to achieve timing closure with conventional design flows. Second, the large number of possible gates on a single chip poses a serious productivity challenge.

One solution is leveraging existing gates through libraries of reusable building blocks and related design reuse methodologies. The other is adopting an automated design flow that increases productivity at a level of abstraction above RTL, greatly accelerating the creation of new building blocks.

Looking more closely at this "Intellectual Property (IP) creation" or "IP authoring" flow reveals two distinctive components: a generation of an executable specification or system-level model of the building block, usually written in the C or C++ language; and implementing this specification into hardware.

For the first time, we are entering into an era of design automation where both of these components are clearly achievable. With newly available, first-generation system-level design tools, designers can easily create a C-based executable specification, analyze its behavior, and implement it in hardware and software without leaving the C/C++ environment. Additionally, they can describe the functionality of systems in the way they are used to thinking about them. These tools permit arbitrarily nested data flow and control flow descriptions. They support timed as well as untimed domains. So, designers can choose the description style best suited for various parts of the system.

Another long-standing issue for system designers is the gap between DSP algorithms originally expressed in C/C++, and the code necessary to express those algorithms in terms of a hardware implementation. Because DSP plays a critical role in many, if not the majority of SoC designs, this gap represents a major productivity sink. Fortunately, a new generation of DSP design tools automates the floating-point-to-fixed-point conversion process, which is the major stumbling block in the current DSP design flow.

Finally, new EDA technology is presently emerging that bridges the productivity void between the C/C++ oriented world of system-level design and the hardware implementation world. The key to this breakthrough is SystemC. This industry standard, created by the Open SystemC Initiative, provides all the mechanisms necessary to describe hardware in a C/C++ programming environment.

Using SystemC hardware datatypes and language constructs, designers are able to refine their original C/C++ code into a form acceptable as input for synthesis. At the same time, they can use their original C/C++ test benches developed during the system specification stage to verify their SystemC designs. The verified SystemC descriptions can then be synthesized directly into a gate-level netlist, a synthesizable VHDL, or a Verilog RTL description. This process eliminates all the arduous labor associated with rewriting C-based system behavioral descriptions into RTL code.

Taken as a whole, this new breed of EDA tools represents a substantial advance in design flow automation, from system-level descriptions written in high-level source code to their final implementation as silicon and compiled object code. Ultimately, it represents the key to rapidly moving SoC-based systems from concept to silicon, in a time when the marketplace will accept nothing less.