Digital ICs

Sept. 5, 2000
Collection Of IP Cores Take Aim At FPGAs With 10 Million Gates A collection of 29 intellectual-property (IP) cores have been qualified for use on the Xilinx...
Collection Of IP Cores Take Aim At FPGAs With 10 Million Gates A collection of 29 intellectual-property (IP) cores have been qualified for use on the Xilinx Foundation and Alliance version 3.1i software development tools. The cores support the company's Virtex II family of high-density FPGAs, which range in capacity up to 10 million system gates. The collection includes general-purpose cores and DSP cores that can also be used on the previously released Virtex and Spartan-II FPGA families.

The cores include four groupings—DSP functions, storage elements and memories, math functions, and basic elements. The DSP group includes blocks such as FIR filters, FFTs, and other functions that allow performance levels of up to 600 billion multiply-accumulate operations per second when overlaid on the Virtex-II architecture. Available IP in the storage area includes parameterized asynchronous FIFOs and single-/dual-port memories.

A complete list of cores can be found on the company's IP-Center web site, All 29 cores are immediately available, and they can be downloaded over the Internet.

Xilinx Inc., 2100 Logic Dr., San Jose, CA 95124; (408) 559-7778;

FEC Chip Cuts Required Bandwidth And Increases Data Throughput Based on the enhanced Turbo Product Code technology (eTPC), the Astro OC-3 forward error correction (FEC) IC lets designers decide what combination and level of benefits works best for their application. With this device, designers can reduce their required bandwidth by two times. Or, they can double the data throughput. The OC-3 also makes it possible to increase range by 40%, reduce antenna size by 30%, reduce transmitter power by two times, or cut the receiver's required noise figure by 3 dB.

The OC-3 suits applications requiring high code and data rates. It can be used in satellite communications, wireless LANs, and wireless digital broadcast applications. Providing up to 3 dB of coding gain, it achieves 200-Mbit/s channel rates. Also, the OC-3 FEC IC integrates a TPC encoder and decoder, and it can be operated in a full duplex mode. It supports block sizes up to 16 kbits as well.

Prototypes are now available. Volume shipping will begin in the fourth quarter. In 1000-unit quantities, the OC-3 costs $100.

Advanced Hardware Architectures Inc., 2365 N.E. Hopkins Court, Pullman, WA 99163-5601; (509) 334-1000; fax (509) 334-9000;

Dual Digital Potentiometer Serves Gigabit Network Transceivers In addition to containing a pair of digitally controlled potentiometers, the DS1845 packs 256 bytes of EEPROM to retain its control settings. Targeted for use with gigabit network transceivers and other systems that need periodic calibration or current-level adjustments, this dual potentiometer reduces system component count and space requirements.

Housed in a 14-lead TSSOP, this dual linear-taper potentiometer comes in three variations: the DS1845-010, 050, and 100. The first packs a 10-kΩ, 100-position and a 10-kΩ, 256-position potentiometer. The second quintuples the value of the second potentiometer. And, the third raises the value of the second potentiometer by an order of magnitude to 100 kΩ.

A serial two-wire interface provides access to data and potentiometer control, and an external Write-Enable pin protects data and potentiometer settings. Two bytes are needed for nonvolatile wiper storage. The DS1845 operates from either a 3- or 5-V supply. It can function over a −40°C to 85°C range, but it can only be programmed from 0°C to 70°C.

Available from stock, the dual nonvolatile potentiometer costs $1.73 each in 1000-unit quantities.

Dallas Semiconductor, 4401 South Beltwood Pkwy., Dallas, TX 75244-3292; Patrick Fedele, (972) 371-3719;

Fast-Cycle 16-Mbit DRAM Targets Portable System Applications Addressing the need for high-density temporary storage in portable systems, a 16-Mbit fast-cycle DRAM known as the MB82D01160/1 offers an asynchronous SRAM interface and an access time of just 90 ns. The FCRAMs employ a nonmultiplexed address input and require a low refresh rate to better fit into applications previously filled by lower-capacity static RAMs.

This memory has an active current of about 30 mA and a standby current of 200 µA for the standard version, and just 100 µA for the low-power version. Both versions can operate from 2.3 to 2.7 V, or from 2.7 to 3.0 V. They function from −25°C to 85°C. Organized as 1-Mword by 16 bits, these memories are housed in 48-contact FBGA packages.

Four versions are available: a 100-ns access time version in both standard and low-power options, and a 90-ns access-time version in both standard and low-power options. In sample quantities, the MB82D01160/1 costs $38 each.

Fujitsu Microelectronics Inc., 3545 N. First St., San Jose, CA 95134-1804; (408) 922-9000;

Bypass Circuits Simplify Fibre Channel System Design A trio of port bypass circuits—the VSC7127, VSC7129, and VSC7124—simplify the design of Fibre Channel systems. As Fibre Channel support circuits, they give designers more flexibility when designing 1.0625-Gbit/s JBODs and disk arrays. They can be used in signal steering applications for Fibre Channel-based disk drives, or to perform on-chip transmit termination. Also, they're pin-compatible with the HDMP-0450, 0451, and 0452 bypass repeater circuits offered by Agilent Technology while enabling the designer to select either a repeater or a retimer.

The VSC7124 is a five-channel bypass element. The VSC7127 and VSC7129 include retiming circuits. Both offer six-port bypass interfaces and the FibreTimer clock-recovery unit, which operates in either a repeater or retimer mode. As a repeater, the block recovers the data and retransmits it to a recovered clock, reducing jitter and latency. In the retimer mode, the recovered data is re-transmitted synchronously to a local reference clock, totally eliminating accumulated jitter but adding some latency to the data. These two models also provide an analog/digital signal detect unit.

All three chips are housed in 44-lead PQFPs and sell for less than $9 each in lots of 5000 units.

Vitesse Semiconductor Corp., 741 Calle Plano, Camarillo, CA 93012; (805) 388-3700;

256-kbit Serial EEPROM Handles Data Transfers At 5 MHz A 256-kbit serial EEPROM known as the X25256 can transfer serial data at up to 5 MHz. It's housed in a BGA package that occupies just 8.4 mm2, which is less than half the space required by an SOIC package. Also, this EEPROM employs the SPI serial interface and operates from a 2.5-V supply.

Its Block Lock capability lets designers lock selected memory blocks within the memory array through a special software register command, preventing unauthorized access to these blocks. This function can add an enhanced level of security in applications such as cell phones or other systems that contain proprietary information.

Housed in an 8-lead SOIC package, the X25256 costs $3.15 each in 1000-unit lots. The XBGA package option costs slightly more. Samples and production quantities are immediately available.

Xicor Inc., 1511 Buckeye Dr., Milpitas, CA 95035; Mike Levis, (408) 546-3317; fax (408) 432-0640;

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