Latest Nios CPU Targets 32-Bit Control Needs

A second-generation implementation of the Altera Nios processor architecture boosts the embeddable CPU core to a full 32-bit implementation. The company enhanced this core to implement many more custom instructions than its predecessor. These custom instructions let designers accelerate a program's time-critical portions.

Designed to fit on most of Altera's Stratix II, Stratix, and Cyclone FPGA families, the Nios II processors deliver performance comparable to an ARM 9 or a PPC 826x processor, yet they're code-compatible with the original Nios cores. The Nios II family initially will consist of the II/f, II/s, and II/e core implementations. The letter defines the level of performance—fast, standard, or economy (see the table). For all three versions, the highest-performance implementations will be on the Stratix II FPGA family.

The fast option delivers the highest performance, about 200 Dhrystone MIPS (DMIPS) when clocked at 175 MHz. It requires a moderate amount of FPGA resources (about 1180 logic elements). The standard version delivers slightly less performance, about 90 DMIPS at 175 MHz, but only needs about 800 logic elements. The economy model provides the lowest performance of the three, 28 DMIPS at 190 MHz, but it also consumes the fewest logic resources on the FPGA—about 400 logic elements.

All three cores share some common architectural elements, such as a 32-bit instruction size, 32-bit data and address paths, 32 general-purpose registers, 32 external interrupt sources, and little-endian byte ordering. Yet they differ in the amount of pipelining in the data path, the size of the level 1 instruction and data caches, the use of hardware DSP support, and the use of branch prediction (dynamic, static, or none for the f, s, and e cores, respectively).

In the first Nios processor, a maximum of six custom instructions could be created to accelerate algorithms. Boosting that number to 256 custom commands, the Nios II cores provide much more flexibility to create user-defined hardware blocks that augment the ALU in the processor.

A portfolio of IP cores supports the Nios II cores. They're available as part of Altera's SOPC Builder tool, which is part of the Quartus II development tool suite.

To tie the IP cores to the Nios processor, the Avalon on-chip switch fabric provides a parameterized interconnect fabric rather than the traditional shared bus structure. Designers only have to craft the interface their peripheral requires without worrying about the complete set of Avalon switch-fabric transactions. The SOPC Builder design tool automatically generates the proper Avalon switch fabric to tie into the interface of each peripheral present in the system.

When developing software to run on the Nios processor, the software development tools from Altera and its partners let designers automatically generate a customized C/C++ run-time environment tailored to the system hardware. Operating-system support is available from several partners, including Micrium Technologies, ATI/Mentor Graphics, KROS Technologies, MiSPO, eSOL Co. Ltd., and Open Source. Nios II development kits are now available.