Programmable Multicore Processor Takes On Multimedia's "Multi" Tasks

DSP applications have a new weapon in the CT3616 programmable multiprocessor engine. Developed by Cradle Technologies, it delivers an aggregate computational throughput of 24 GMACs/s for simultaneous encoding of 16 real-time MPEG-4 video channels (480 frames/s) at SIF resolution and 16 G.711 voice channels.

The CT3616 also can concurrently perform complete IP packet encapsulation (RTP/UDP) thanks to an integrated 10/
100-Mbit/s Ethernet media access controller (MAC). Additional on-chip resources include an integrated hard-disk IDE or compact-flash storage interface as well.

With such multitasking capability, designers can turn the processor into a 16-channel digital video recorder at a cost of $5.50 per channel. This translates into significantly reduced system hardware and much lower cost for surveillance and other applications.

The CT3616's 16 programmable general-purpose 32-bit DSP engines can be programmed for myriad applications. This includes real-time D1-quality H.264 main profile video encoding, which can be used in next-generation IP TV head-ends and media gateways.

The basic chip architecture splits the processing into two main blocks known as Quads (see the figure). Each Quad contains 128 kbytes of shared data memory, a 32-kbyte shared instruction cache, four general-purpose CPUs, and eight DSP engines.

The processors can operate at clock speeds of up to 375 MHz, while the internal global bus will reach 500 MHz. Each Quad also features 72 programmable I/O lines, divided into nine pin groups. In addition to the MAC and the IDE storage interfaces, the CT3616 features a 64-bit, 333-MHz double-data-rate (DDR) SDRAM memory controller; a 32-bit/MHz PCI port; and an ITU-r 601/656 video port.

A complete development tool set incorporates version 5.0 of Cradle's software development kit and the RDS digital media development platform. Featured in the kit is Inspector, a multicore development and graphical debugging environment that can handle up to 24 processors simultaneously. CLASM, a C-based intermediate-level compiler for timing-critical DSP task optimization, is included too.

Two scaled-down versions of the chip are available. The CT3608 packs eight DSP and four RISC cores and has fewer I/O pins, while the CT3612 brings 12 DSP and six RISC cores to the table.

The CT3616 will sample in June. Prices start at $53 each in lots of 10,000. In similar quantities, the CT3608 starts at $37.