Advanced Processors And Media Engines Crank Up The Heat At Hot Chips 17

Aug. 4, 2005

It's the dog days of summer, and the 17th Annual IEEE Hot Chips Conference will spotlight some sizzling technologies. Scheduled for August 15 and 16 at Stanford University in Stanford, Calif., the conference will examine specialized processors, reconfig

Dave Bursky

The entire opening session will focus on the high-performance Cell processor jointly designed by IBM and Toshiba, as well as a previously undisclosed Toshiba audio/video support chip. (Sony selected the Cell for its next-generation PlayStation game console.) A specialized processor session on Monday afternoon will look at a processor for aggregation from Intel, a Fibre Channel switch from Cisco, and a pattern-matching engine by IBM.

Additional sessions on Monday will highlight advanced technologies and media processors. In the advanced technology session, Luxtera will detail photonically enabled CMOS structures. Also, a team of Japanese researchers from ISTEC, NICT, Nagoya University, and Yokohama National University will describe a 40-GHz single-flux-quantum switch scheduler.

The media processor discussions will examine a real-time H.264 HD chip from Telairity Semiconductor, a next-generation audio engine from Tensilica, a super-pipelined media engine from Philips, and a scalable DSP family from Cradle Technologies.

The second day will start with a look at more specialized processor architectures--a networked multiple-instruction/multiple-data processor for particle physics developed by the University of Heidelberg, and a prototype of the TRIPS processor (first detailed at last year's Hot Chips conference) by the University of Texas in Austin.

Reconfigurable processors will be the focus of the midday sessions. Toshiba's researchers will describe a configurable 1-GHz processor core. Engineers from Stretch will detail a software-configurable processor. IPFlex will show off a dynamically reconfigurable processor with 376 32-bit processing elements.

Furthermore, Ascenium will unveil a continuously reconfigurable architecture. Altera will describe its NIOS II soft CPUs. Xilinx will reveal its configurable systems-on-a-chip with its Virtex 4 FPGA architecture. And, the University of California at Berkeley will offer the design of the BEE2 high-end reconfigurable computing system.

A session on processors and systems will wrap up the conference. Intel will describe its Paxville Xeon microprocessors, the TwinCastle multiprocessor Northbridge server chip set, and a dynamically optimized power-efficient schema based on the company's Foxton technology.

For the latest program and registration details, go to www.hotchips.org. Also, check out the link to the Hot Interconnects conference, which follows the Hot Chips event.

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.