Power = Performance = Price In Wireless And Consumer Technologies

March 1, 2007
Most large-scale chips for wireless, communications, and networking contain at least one embedded core for control or signal processing or both. As processing speeds have increased to keep up with the demand for the latest standards, protocols, and app

Most large-scale chips for wireless, communications, and networking contain at least one embedded core for control or signal processing or both. As processing speeds have increased to keep up with the demand for the latest standards, protocols, and applications, these embedded processors have had to kick up their processor speeds.

But this translates into increases in power consumption that can compromise or even become a knockout factor for a battery-powered device. Furthermore, as performance goes up, price usually follows. The goal is to find a way to balance the various performance, power consumption, and price needs with the available technology.

Designed for communications chips and consumer products, the 32- and 64bit RISC cores from MIPS Technologies let designers trade off one feature for another to achieve that balance. They're available in register transfer level (RTL) form that isn't tied to any particular process technology. Balancing the core supply voltage (1.2, 1.0, or lower) and CMOS feature size (down to 65 nm) usually resolves the competing needs.

MIPS has a wide range of core designs. Its 32-bit M4K uses only about 35,000 gates and fits in a 1-mm2 area, while the company's larger 64-bit designs have upward of 500,000 gates. The designs can accommodate clock speeds to 1 GHz. And through the CorExtend technology, some cores even have DSP instruction set extensions that can eliminate a separate DSP chip in some designs.

With the cores' clock gating capability, unused parts of the circuitry can be shut down for huge savings in power consumption. The cores also operate at clock speeds down to 0 Hz. With power consumption proportional to speed, speed can be controlled to achieve the desired level of power usage. At 0 Hz, only the leakage current is using power.

The cores can even be used in smart cards that derive their power by induction from the reader. This low power consumption lets the chip boot, execute the communications protocol, and transfer the data in the card memory to the reader.

Atheros Communications' 802.11n chips, Broadcom's digital TV chips, Entropic Communications' c.LINK-270 coax cable home networking solution, LG Electronics' portable navigation device, Raza Microelectronics' personal navigation device, and Samsung's T-DMB mobile TV chips all use MIPS cores.

MIPS Technologies www.mips.com

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