Suppliers Deliver Low-Cost 32-Bit Arm Architecture

March 23, 2012
Freescale is the first out the chute with the Kinetis L based on Arm's latest Cortex-M0+ architecture targeting low power, low cost applications.

Arm’s Cortex-MO+ ups the ante on the Cortex-M0 architecture, which includes a trace buffer for debugging as well as faster, single-cycle I/O interfaces (see the figure). The chip also has the same Thumb-based instruction set as the Cortex-M0. This subset of the instruction sets is implemented on the higher-end Arm architectures, including the Cortex-M3 and Cortex-M4, providing upward migration.

Arm’s Cortex-M0+ architecture includes a micro trace buffer that shares on-chip memory. Developers can trade off buffer size with application storage.

The Cortex-M0+ requires only 12k gates in its smallest configuration. Its two-stage pipeline uses fewer flip-flops and has a two-cycle branch turnaround. Instruction fetch has been optimized to minimize flash memory access to reduced power requirements. Also, the Cortex-M0+ reduces power consumption to 9 µA/MHz while delivering 1.77 CoreMark/MHz. It can run at low frequencies, and the architecture uses extensive clock and power gating to preserve power. The combined efficiency makes the Cortex-M0+ significantly better than 8- or 16-bit microcontrollers.

Developers now have access to trace capabilities like the embedded trace module (ETM) found in higher-end Arm architectures. The micro trace buffer (MTB) keeps its circular buffer in shared SRAM rather than dedicated memory. The amount is programmable so a smaller buffer can be used when necessary or when applications need to utilize most of the SRAM. Even 30 or 40 words is sufficient since the trace facility only uses two words when a branch occurs. MTB access uses the regular serial debug interface, so no additional pins are required.

Meanwhile, Freescale’s Kinetis Cortex-M4 line now adds the Kinetis L Cortex-M0+ series. Freescale skipped the Cortex-M3 because the Cortex-M0+ and low-end Cortex-M4 chips that lack floating point support can cover this area. The line employs Freescale’s 90-nm technology and even targets its own 8-bit S08 line with pin-compatible KL0x chips. The KL1x chips are pin-compatible with the Cortex-M4 Kinetis chips. Freescale’s Eclipse-based Code Warrior integrated development environment (IDE) and Processor Expert tools support the chips. Several third-party tools also support the entire Kinetis line.

Designs have been moving to 32-bit platforms from 8- and 16-bit chips as the 32-bit chips hit the same price and power points while delivering more performance and a better development environment. A significant amount of legacy code is in assembler, but migration to 32-bit becomes more interesting as code is moved to C and C++.



Sponsored Recommendations

Near- and Far-Field Measurements

April 16, 2024
In this comprehensive application note, we delve into the methods of measuring the transmission (or reception) pattern, a key determinant of antenna gain, using a vector network...

DigiKey Factory Tomorrow Season 3: Sustainable Manufacturing

April 16, 2024
Industry 4.0 is helping manufacturers develop and integrate technologies such as AI, edge computing and connectivity for the factories of tomorrow. Learn more at DigiKey today...

Connectivity – The Backbone of Sustainable Automation

April 16, 2024
Advanced interfaces for signals, data, and electrical power are essential. They help save resources and costs when networking production equipment.

Empowered by Cutting-Edge Automation Technology: The Sustainable Journey

April 16, 2024
Advanced automation is key to efficient production and is a powerful tool for optimizing infrastructure and processes in terms of sustainability.


To join the conversation, and become an exclusive member of Electronic Design, create an account today!