NXP LPC1200 block diagram
LPCXpresso development kit
NXP has been making good use of Arm's Cortex-M0 architecture (see 32-Bit Architecture Changes The Power Game For Micros). The NXP LPC4000 combined a Cortex-M0 with a Cortex-M4 (see New Platform Approaches Deliver Top Digital Designs In 2010). The Cortex-M0 has a very compact Thumb 2 instruction set.
The new 30MHz LPC1200 (Fig. 1) targets industrial control, white goods and home automation applications. It has robust i/O interfaces with high noise immunity and 8kV ESD (electrostatic discharge) protectio. It also includes a low power state machine for peripheral control that can operate while the CPU is asleep. It can also off load the CPU from many peripheral control chores. It has 8 Kbytes RAM and up to 128 Kbytes of flash with a 512 byte page size. The ROM contains peripheral drivers and a deterministic divide routine (~100 cycles). The Cortex-M0 has a multiply but no divide instruction.
The chip has 55 GPIOs, two 32-bit timers, two 16-bit timers, and a real time clock. Peripherals include DMA support, two UARTs, an SPI/SPP port, and an I2C port. There is a CRC engine. Analog peripherals include an 8-channel, 10-bit ADC and two comparators with 32 Vref levels.
The system state machine is similar to the one on the LPC4000. It comes with a number of configuration templates that allows operation even while the processor is asleep. The system allows configurations such as the comparators controlling when the ADC will run.
The chip has a built-in 12 MHz oscillator with 1% accuracy. It has an industrial (-40C to +85C) operating range.
Pricing for the LPC1200 starts at $1.25 with 32 Kbytes of flash memory. It is available in LQFP48 and LQFP64 chips. The LPCXpresso development kit (Fig. 2) is priced at $29.95. It includes the free LPCXpresso IDE.
The LCD12Dxx version of the chip adds support for a 40x4 segment LCD display. It will be available later this year.
