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Subthreshold Cortex-M4F Design Sips Less Power Than Cortex-M3

Jan. 22, 2015
Ambiq Micro’s Apollo family of ARM Cortex-M4F microcontrollers draw less power than the typical Cortex-M3 by using a subthreshold voltage design.
1. Leakage becomes critical as designs approach subthrehold voltages around 0.3 V.

Ambiq Micro’s Apollo family of ARM Cortex-M4F microcontrollers utilize a subthreshold voltage design that allows the chips to draw less power than the typical Cortex-M3 microcontrollers. Technology migration from 5V to 3.3V to 1.8V moves towards a near threshold voltage of 0.5 V. Subthreshold voltage for CMOS is 0.3 V.

Energy consumption for threshold voltage designs is dominated by dynamic energy (Fig. 1). Leakage energy becomes much more important near subthreshold designs. The overall dynamic energy factor improvement at 0.5 V is 13 times and a whopping 36 times at 0.3 V. Unfortunately reaching these points is not easy.

The conventional threshold digital logic design use amplification to handle the logical on and off states. Unfortunately with a subthreshold design there is not enough voltage to turn off a transistor. On the other hand, there are other ways to implement logic and this is include’s Ambiq Micro’s Sub-threshold Power Optimized Technology (SPOT).

Similar approaches have been used for applications like pacemakers and RFID tags since the 1970’s. Ambiq Micro has also used the approach for its low power, real time clocks (RTC). One aspect of these designs is their simplicity compared to something complex like an ARM core. The current crop of chip design tools allow subthreshold implementations to address the more complex chips.

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Part of the challenge Ambiq Micro faced was the poor transistor simulation accuracy at low voltages. This was not an issue for higher voltages where simulation models matched implementation details more closely. Second, the sensitivity of the design needs to be significantly improved compared to conventional logic designs. Another challenge with a subthreshold design is the increased variance due to temperature change.

Testing is also an issue because systems need to be checked for nanoamp or picoamp values. Fortunately very low power designs are now the norm even if they tend to be for more compact systems like Cortex-M0 architectures.

2. The Apollo Cortex-M4F architecture looks like conventional microtrollers but its core is implemented using a subthreshold design.

Addressing the design techniques for the Apollo Cortex-M4F (Fig. 2) needed to address not just digital transistors but also the analog support since the chips include ADC and DAC peripherals. System design changes required selective modification from threshold to subthreshold transistor implementations. RAM and flash designs were not changed as the optimization of the processor core offered the most power performance improvements. The design approach was to convert the standard design to a subthreshold design where possible and where the power advantages were significant.

The resulting system employs buck converters to move from an input operating voltage from 1.8 V to 3.3. V to the internal subthreshold voltages. The peripheral interfaces operate at the input voltage so conventional external devices can be utilized. The result is a 30 µA/MHz active current operation. Sleep mode hits 100 nA. The chips were created using a conventional CMOS design process.

Very low power comes at a cost but not a lot. Pricing for the chips starts at $1.50. The power savings is on the order of a factor of ten putting the Cortex-M4F functionality on par with the more conservative Cortex-M3 designs. 

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