72-Core Platform Targets Networking Chores

Tilera’s TILE-Gx72 packs in 72 1.2 GHz 64-bit cores (Fig. 1). That translates to 80 GHz of computing power. It targets high end networking applications with its mPIPE engine. It is the big brother to the recently announced 9-core TILE-Gx9 (see “Multicore Chip Downsizes”).

The TILE-Gx72 can deliver up to 120 Mpackets/s for ingress and egress. The mPIPE can drive a mix of Ethernet ports delivering up to 100 Gbits/s. This includes eight 10 Gbit/s XAUI ports to thirty two 1 Gbit/s Ethernet ports.

The mPIPE offloads the processor cores. Its C programmable engine handles packet parsing and classification. It also does load balancing distributing traffic to different cores as necessary in a cache coherent environment. The packet buffer management is flexible with configurable modes, buffer sizes and queues. The resources are virtualized and the support has zero overhead on the processor cores. The mPIPE supports Broadcom HiGig and Marvell DSA protocols. 

Throughput is the name of the game and Tilera’s internal fabric is just the start. It can be configured for a variety of PCI Express ports including 6 x4, 2 x4 or 2 x8 lanes.  The PCI Express support is impressive. It has a 99% efficiency. Off-chip memory is accessible via four 1866 DDR3 controllers attached to the fabric.

Encrypted traffic is handled by a pair of MiCA engines that run up to 80 threads. This translates to 40 Gbits/s of crypto traffic and 45 Ktransactions/s using RSA public key support. The MiCA engine also supports compression and decompression.

The TILE-Gx72 comes in a 45mm by 45mm BGA package and requires less than 60W. This breaks the pin-compatibility found in the 37.5mm by 37.5mm BGA packages used by the TILE-Gx9, TILE-Gx16, and TILE-Gx36 (see “Many Core Systems Handle Network Processing Chores”).

The family (Table 1) shares a common programming environment. It makes partitioning easier so a group of cores can handle a particular job. An intrusion detection system (IDS) that delivers 14 Gbit/s throughput and handling 12,000 rules will require 70 cores or 90% of the top end TILE-Gx72. A simpler, network security processing system needs only 10 tiles to handle 40 Gbits/s of SSL3 record processing. This would fit on a smaller chip or allow the TILE-Gx72 to handle other chores. For example, a system can support a range of multimedia codecs and perform streaming encode and decode operations.

Table 1

The TILE-Gx72 represents an impressive performance increase allowing it to handle larger applications than earlier chips. Upward migration is easy because of the common programming environment.