Low Power, Single-Chip APU Delivers High Performance

April 24, 2013
AMD has delivered a single chip, APU (accelerated processing unit) that uses the latest 2 GHz Jaguar core and a Radeon 8000 GPU.

Design West 2013

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The single-chip Embedded G-Series accelerated processing unit (APU) family from AMD uses the company’s latest 2-GHz Jaguar core and Radeon 8000 graphics processing unit (GPU). Used on AMD’s higher-end platforms, the Jaguar supports a 40-bit physical address space and doubles the floating-point bus width to 128 bits. Jaguar also doubles the load/store bandwidth to 16 bytes/cycle, compared to the Bobcat architecture.

AMD’s original APU was a multichip solution that integrated the CPU and GPU on a single chip (see “APU Targets Embedded Applications”). According to some rumors, Sony’s future Playstation 4 will use an APU. Single-chip x86 platforms have been available and popular, but typically the video support was limited. The Radeon GPU is a full-function solution that also can be used for computation chores using OpenCL support. During Design West at 2013 in San Jose, AMD exhibited the 25- by 25-mm package in compact, fanless designs with some impressive graphics (Fig. 1).

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Figure 1. AMD’s Embedded G-Series APU chips use only 600 mm2 of space. Versions with a TDP from 9 to 25 W are available.

The chips will be available in a range of configurations with a thermal design power (TDP) from 9 to 25 W. Each chip incorporates a multicore GPU along with a new features like multimedia support for low-latency wireless displays. Also, each chip is combined with an Enhanced Universal Video Decode (UVD) Engine 4.2 and Video Compression Engine (VCE) 2.0. And, the Embedded G-Series supports standard display interfaces such as HDMI, DVI, LVDS, and VGA and can manage two displays using the DisplayPort 1.2 interface.

The 28-nm Embedded G-Series APU architecture uses four cores to support four threads, which is comparable to Intel’s dual-core Atom with hyperthreading (Fig. 2). It has one x4 and four x1 PCI Express links. The 2-Mbyte L2 cache is shared between all cores. The DDR3-1600 interface supports two small-outline dual-inline memory modules (SO-DIMMs). Each chip supports double-data rate (DDR) power states (P-states) to help reduce power requirements. Error correction code (ECC) support will allow the chips to be used in secure or high-reliability applications.

Figure 2. The G-Series APU supports PCI Express and up to two video displays. It also incorporates audio and storage interfaces.

The Embedded G-Series chips have a wide selection of peripheral interfaces but use off-chip networking support that typically will be linked via PCI Express. A 6-Gbit/s SATA v3.x interface provides storage support. There also is support for LPC, SPI, USB 2.0/3.0, and an SD reader. The chips boast encryption acceleration and a Security Asset Management Unit (SAMU) 2.1 as well. They support a variety of operating systems including Windows 8, Linux, and Android. And, the use of the Radeon 8000 CPU architecture will simplify video driver support.

AMD has only announced the chips so far, but they will show up in new designs. There likely will be a variant for GizmoSphere, which currently has a multichip APU implementation (see “Embedded GizmoSphere APU Delivers Over 52 GFLOPS”). It looks like an ideal match for AMD’s server group, SeaMicro, which started with the SM10000 and its 512 Atom cores (see “512 64-bit Atom Cores In 10U Rack”). The SeaMicro fabric chip has x4 PCI Express processor interfaces.

The Embedded G-Series will find a home in a range of application areas from server message block (SMB) storage to in-vehicle infotainment systems. The security and ECC support will open some new doors in the casino gaming markets where APUs are already being used. The chips’ compact size and low power requirements will allow them to be used in rugged tablets and other mobile applications. They come with industrial temperature range so they can be incorporated into automotive and process control applications as well.

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William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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