Platform Security Processor Protects Low Power APUs

May 7, 2014
AMD's Platform Security Processor (PSP) is being incorporated into its latest line of low power Accelerated Processing Units (APU).

AMD's Platform Security Processor (PSP) (Fig. 1) is being incorporated into its latest line of low power Accelerated Processing Units (APU) that combine CPU and GPU cores on the same chip (see “APU Blends Quad Core x86 With 384 Core GPU”). These include the “Beema” and “Mullins” chips based on the Puma+ x86 cores that are combined with GPUs based on AMD's Graphics Core Next (GCN) architecture. While this is the latest GPU technology these chip families do not employ the latest Heterogeneous System Architecture (HSA) that provides a unified virtual memory environment (see “Heterogeneous System Architecture Changes CPU/GPU Software”).

Figure 1. AMD's Platform Security Processor (PSP) is based on an ARM Cortex-A5 that supports the ARM TrustZone technology.

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The PSP is based on an ARM Cortex-A5 core (see “Cortex-A5 Kit Targets Mobile Multimedia Applications”). This implements ARM's TrustZone technology that has been utilized in a wide range of ARM cores. In this case though, it is protecting the x86 core. This secure core boots first using its own ROM and SRAM and verifies the code that boots the x86 core. Custom OS support is available from Trustonics. The PSP's cryptographic co-processor can support x86 applications to secure off-chip storage.

Security is not the only new features found in the Beema and Mullins chips. The energy aware battery boost technology exploits race-to-idle behavior. In many cases, running faster for a shorter period of time is more power efficient that running for a longer period of time using a lower power setting. This is on top of a 20% lower idle power level.

Beema and Mullins (Fig. 2) are built on 28-nm technology. Beema targets entry level notebooks while Mullins is designed for tablets. The have up to four x86 Puma+ cores and a 128 GCN Radeon GPU. Puma+ uses a 2-wide our-of-order execution unit. The chips have a 64-bit memory interface.

Figure 2. Beema and Mullins employ 28-nm technology with up to four x86 Puma cores.

These chips will likely host Windows operating systems although they can easily handle Android and Linux as well. The chips support DDR3 memory. The Beema A6-6310 clocks at 2.4 GHz with four cores and a 15 W TDP while the low end, E1 Micro-6200T Mullins runs at 1.4 GHz using only 2.95 W TDP with a pair of cores.

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William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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