Read this article online.

Every FPGA shipped today is conservatively rated. The clock frequency on the datasheet is set so a worst-case die, at the worst voltage corner and temperature near the end of rated life, still meets timing. For most dies in their early lives, that rating is far below what the silicon could actually deliver. 

Vendors do this because static guardbanding is the only way to make a reliability promise that survives the field^9,10 and the cost is real: performance and energy efficiency persistently left on the table. With bias-temperature instability (BTI) and hot-carrier injection (HCI) now well characterized in FinFET technologies,^1,2,4 that cost is becoming hard to justify. This article describes a closed-loop, learned frequency controller that reclaims most of the static margin in a device's early years, hands it back as it ages, and stays inside the reliability envelope at every step.