Interview: Forte's John Sanguinetti Tackles Trends In SoC Synthesis

Systems designs are getting larger and more complex has foundries churn out chips using ever finer geometries. The challenge for developers is to deliver solutions that can be built without errors. This means using high-level design languages and tools plus extensive simulation of the design to make sure a design is correct before it ever gets to the fab.

I talked with John Sanguinetti, Chief Technology Officer, Forte Design Systems, about these challenges and trends.

Wong: What trends are you seeing in SoC synthesis simulation?

Sanguinetti: I presume the question should be “What trends are you seeing in SoC synthesis?”

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The trends I see are that people are doing more varied design styles with High-level synthesis. We are seeing completely control-dominated designs being done with HLS, as well as completely data-path dominated designs. It used to be that most designs done using HLS were relatively straightforward data-path designs, like DCT (Discrete Cosine Transform) blocks, or filters. Later, designs like Viterbi decoders, which were a mix of control and data path become common. For the past couple of years, a wider variety of design types are being done with HLS, to the point where now exclusively control designs, like interface controllers, are commonly being done with HLS. We see this trend continuing, with some truly surprising designs which have very complicated control structures being done with HLS.

If the question is “What trends are you seeing in SoC simulation?,” then the answer is different, and I’m not sure I have a great insight. What I have seen, which may be only anecdotal, is that simulation is getting harder with the complexity of new SOCs. There is so much functionality in a big SOC, that doing a very complete job of covering the design with simulation is nearly impossible. We are seeing the DV teams getting bigger and bigger. Formal analysis is being used more and more, but this is mostly stuck at RTL. Doing verification at the system level, which is simulation, involves using constrained random test generation more and more, but the tools are not keeping up. In general, there is a real need for the good RTL verification tools to move up a level of abstraction to the system level.

Wong: What kinds of challenges are designers now facing designing large SoCs?

Sanguinetti: A large SOC contains a significant number of IP blocks that come from somewhere outside of the design group. It also contains a lot of memory, and it contains a reasonable amount of new logic blocks. Verifying that all this works together is very hard. Doing simulation of a virtual prototype is limited by simulation speed. Creating an FPGA prototype is difficult due to the inherent mismatch of the underlying technology of the FPGA and the SOC. Hardware simulation is expensive and takes a non-tricial amount of work. Doing an FPGA prototype is currently the way to get the most capable verification prototype, but it is difficult to map the ultimate design to the FPGA board.

Aside from verification, managing the power requirements of a large design is difficult, since a design team does not control all of the blocks that go into the SOC design. If you can turn off a complete IP block, then you don’t necessarily have to know much about its internals, but if you have to do some interaction with the block to put it into a power-saving mode, you have to know something about it. If the IP block is soft IP (that is delivered in RTL), then running a power-optimization tool on it before synthesis is risky, and likely to lead to contention with the IP vendor if problems arise.

Wong: What solutions are available to overcome these challenges?

Sanguinetti: High-level synthesis is getting a lot better, and in the process has lessened some of the problems, particularly with regard to creating FPGA prototypes. It is now much easier to take a design intended for an SOC and retarget it to an FPGA. Doing this, the RTL itself is not being verified, but the higher level design is, and that is what is important. HLS is also doing a much better job producing power-optimized RTL, doing optimizations that power-optimizing post-processing tools can’t.

Some work is being done with assertions in SystemC, and this has promise. The SystemC Verification library (SCV) is making a good beginning at getting the sophisticated test bench creation tools available at RTL up to the higher level of abstraction.

Wong: How has the industry evolved from when you developed VCS? What about high-level synthesis?

Sanguinetti: When we created VCS, I did not believe that 10 years hence, people would still be designing hardware at RTL in Verilog. Here we are 20 years later, and high-level design is still in the minority. The industry has not evolved all that fast. Part of the answer as to why that is the case lies in the extensive infrastructure that has grown up around RTL design. There are a lot of tools that use RTL Verilog as either input or output. One of the reasons that high-level design and synthesis has not grown more quickly is the lack of such a rich design environment at the higher level.

On the other hand, the value proposition of high-level synthesis is getting more compelling as design complexity increases. It is simply inevitable as design sizes increase. Automatically generated RTL is higher quality than hand-generated in the vast majority of cases. Since high-level code is so much more flexible than RTL, making modifications is an order of magnitude easier. While design efficiency is compelling, nearly all of our HLS customers will tell you that the biggest benefit to using high-level design and HLS is the ease with which previously designed blocks can be repurposed for new implementations.

Wong: Is there room for more breakthrough technologies? If so, where what part of the design flow?

Sanguinetti: There is always room for new technologies, but they are getting harder to do. This is primarily because a new product has to interface with so many other products in the design flow, that there is a lot work to do which has little to do with the primary innovation in the new tool. Verification looks to me to be the area where the need is greatest, and the status quo is not all that good. I hope that breakthroughs can be made in formal analysis at the higher level. I know there is a lot of academic work going on there, and I think there is opportunity to translate some of that to the design world.

Wong: What advice can you offer readers of Electronic Design?

Sanguinetti: My advice is to take high-level design seriously. While there are some projects where it is not optimal, the vast majority of design projects can benefit from high-level design. Business as usual is simply not tenable as design sizes increase. The move to a higher level of abstraction is inevitable, and the only real question is what form will that abstraction take. The most commonly used language now is SystemC, and though it is not perfect, there is a lot of value in using a standard that is supported by many tool and IP vendors.