ARM has released a new set of tools designed to streamline the process of building silicon with one or more Cortex cores (see the figure). The tools include ARM Socrates Design Environment (DE), Corelink Creator, and Coresight Creator.
It used to take months to turn ARM IP into a product and that is assuming a relatively easy integration with third-party IP. The new tools look to cut this process to a few days with basic system design started within an afternoon.
The starting point is ARM Socrates DE and its IP Catalog. This includes the usual ARM IP, including Cortex CPU cores as well as GPU cores. The catalog uses IEEE standard IP formats allowing third-party IP to be included. Design-rule checks (DRC) help validate the design during system construction. DRC support means automatically generated RTL and design specifications will work.
Part of the challenge for larger designs is coming up with something that can actually meet all the design constraints, including power and timing.
ARM Corelink Creator provides the interconnect between cores and IP. This can be relatively simple for a single core and a few peripherals or a more complex environment designed to support multiple CPUs, GPUs, DMAs, and so on. It supports the NIC-450 hierarchy of NIC-400 interconnects delivering a deadlock-free system. It can also handle multiple power and voltage domains that are common on large and small systems.
The final piece to the puzzle is provided by ARM Coresight Creator. Coresight is the debug support found in most Cortex-based microcontrollers and microprocessors. The debug and trace support can vary and Coresight Creator allows developers to select and configure the on-chip tools they desire. The process was complex because often hundreds of registers and interface ports needed to linked by hand. Changes were time-consuming and error-prone. Coresight Creator automates this process, reducing time to market and providing an error-free debug design.