The Belgian-based international nanotechnology research organization imec is making significant progress toward 7-nm and below semiconductor process technologies. The organization recently announced the development of a manganese (Mn)-based self-formed barrier (SFB) process that significantly improves interconnect resistance performance, it described a cryogenic etching method that protects the surface of porous ultralow-k dielectrics to minimize capacitance, and it said it is collaborating with Dow Corning on 3-D IC packaging technologies.
Ludo Deferm
Courtesy of imec
In an exclusive interview at SEMICON West in July, Ludo Deferm, executive vice president for business development at imec, elaborated on these achievements. “For scaling from the 20- to 16- to 14- to 10- to 7- and to 5-nm nodes, of course it’s necessary that you also can increase the density on the interconnect level,” he said. “And that’s not so straightforward.” The difficulties center on the interconnect resistance and on the capacitance between the copper lines, which combine to increase RC delays.
The increased resistance, Deferm noted, results from scaling down the damascene lines, and it increases more than linearly because of the requirements of the barrier—such as TaN/Ta—which result in increased loss of the Cu cross-sectional area. imec’s research, he said, indicated that Mn formed a much smaller barrier that attains a significant 45% improvement in RC performance.
These results were achieved in cooperation with imec’s key partners in its core CMOS programs: GLOBALFOUNDRIES, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK Hynix, Fujitsu, and Sony.
Regarding the Mn technology, Deferm said, “Of course, it has to be further proven for yield, but we have already looked at reliability, barrier integrity, et cetera, and it looks quite good” as a solution for the 7-nm node.
While the Mn SFB work focuses on the R part of the RC equation, imec is addressing the C term with its research into cryogenic etching. When scaling, Deferm said, “it’s not only the metal line widths you want to reduce, but you also want to reduce the spacings between them. And of course, reducing the spacings increases the capacitance between the metal lines.”
To control the increase in capacitance in deeply scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, explained Deferm, plasma etching exposes the dielectrics to ions that penetrate into the porous substrate, resulting in carbon depletion and driving k values, and hence capacitance, up.
“For really small pitches, the problem of capacitance is crucial,” Deferm said. “What we tried out is something completely different: cryogenic etching or low-temperature etching.” By applying very low temperatures during etching, imec found that a condensation in the pores protects the low-k material. imec demonstrated the method on a porous organosilicate film.
Deferm described the cryogenic etching research as at the evaluation stage. Work is still ongoing in determining at what temperatures the condensation phenomenon occurs. If it occurs at higher temperatures, the cost of production equipment could be lower.
Deferm also commented on imec’s research into 3-D ICs. The organization is comparing different approaches, he said, including 2½-D solutions using interposer technology. But true 3-D implementations will employ high-density TSVs.
Deferm explained that one step in the TSV fabrication process involves wafer thinning which, in turn, requires a carrier wafer. “You have to glue the existing wafer to the carrier wafer,” he said. “But also you have to release it afterwards”—when the thinned wafer with high-density TSV’s is relatively weak. Thermal debonding treatment, he said, can impose too much stress, “so we have to go to room-temperature debonding mechanisms.”
To that end, imec is working with Dow Corning, an innovator in silicones and silicon-based technology and among the newest member organizations to join imec. Dow Corning’s Temporary Bonding Solution aims at simple bonding/debonding using a bilayer concept comprising an adhesive layer and a release layer. The technology enables room-temperature bonding and debonding processes based on standard manufacturing methods. During the collaborative effort on the project, which Deferm said could take about a year, imec will provide feedback that could result in Dow making changes in the materials it uses. “We need around a year to really understand all the phenomena,” he said.
In conclusion, Deferm said, “We want to be at the forefront of the new technologies. There are still a lot of challenges for the future in all areas—from device to interconnect, to 3-D, to systems and test.”