IJTAG, heterogeneous integration headline ITC

Nov. 20, 2015

IJTAG and heterogeneous integration were two of many points of emphasis at the 2015 International Test Conference held recently in Anaheim, CA. Vice General Chair Ron Press of Mentor Graphics cited the energy of this year’s event as not just stemming from the technical program, but also from the keynotes and poster sessions. The poster sessions, which spanned four hours over two days in the exhibit hall, offered plenty of time for networking—a key request of attendees, according to Press.

Program chair William Eklow of Cisco concentrated on the energy of the panel sessions—citing as an example the panel on 1149.1-based standards spanning both IC and PCB technologies. The panels and technical sessions, Eklow said, covered the gamut from design-for-test to yield optimization.

Karim Arabi delivered the ITC opening keynote speech titled “Brain-Inspired Computing.” Arabi, vice president of engineering at Qualcomm, suggested the brain could serve as a model for a massively parallel, power-efficient, heterogeneous computer.

On the second day of ITC, Andrew B. Kahng, a professor at the University of California at San Diego, addressed ITRS 2.0, a version of the semiconductor industry’s International Technology Roadmap for Semiconductors. ITRS 1.0, he said, was bottom-up, with a focus on what can be made. In contrast, ITRS 2.0 is top-down applications-driven, with emphasis on what will be made, with markets in the driver’s seat. ITRS 2.0 takes into account mobility/smartphone, datacenter/microserver, and Internet of Things/smart object application areas.

And as part of the concluding day of the conference, William R. Bottoms, chairman of Third Millennium Test Solutions, delivered a talk on ensuring reliability in the era of heterogeneous integration. Cost-effective test solutions, he said, will require intelligent redundancy and continuous test while running.

Among exhibiting companies, Synopsys highlighted slack-based cell-aware test for FinFETs and advanced nodes, introduced new ATPG technology that runs 10x faster with 25% fewer patterns, and noted that its test tools are certified in accordance with ISO 26262 for automotive applications. Mentor Graphics also highlighted its test solutions for the automotive market.

Astronics touted its solutions for semiconductor testing, including the ATS 503X Series massively parallel system-level testers and ActivATE IDE and runtime software. The company reports that it has tested more than 5 billion devices.

Advantest featured its CloudTesting Service, an on-demand service providing cloud-based test intellectual property (IP) accessible via a desktop-sized testing terminal.

Marvin Test Solutions highlighted its PXI-based TS-960 semiconductor test platform. In a corporate forum presentation, director of marketing Mike Dewey described the PXI modular architecture as offering a compact footprint with high channel density and high power for digital and mixed-signal test.

Presto Engineering highlighted its expanding capabilities in RF and optical test. The company also reviewed its partnership, announced earlier this year, with INSIDE Secure, a provider of embedded security solutions for mobile and connected devices.

Big data was a key focus at ITC, with PDF Solutions demonstrating its Exensio data-analytics platform for semiconductor yield improvement. And Optimal+ showcased its big data solutions that enable fabless companies and IDMs to derive intelligence from their semiconductor operations. Optimal+ also sponsored a lunch presentation in which Marc Jacobs, vice president of engineering operations at Marvell Semiconductor, discussed Marvell’s use of Optimal+ in its manufacturing operations.

And yieldWerx, a provider of yield-management semiconductor solutions, said it has deployed yieldWerx Enterprise at QuickLogic to streamline test and yield-management processes, thereby enhancing quality, improving engineering productivity, decreasing test cost, and reducing time to market. yieldWerx Enterprise’s real-time data-cleansing, mapping, and lot-genealogy capabilities allow QuickLogic to focus on device characterization and root-cause analysis. This real-time capability makes the QuickLogic staff more efficient in finding systematic operational issues that impact yield and quality—leading to faster production ramps, greater manufacturing yields, and lower manufacturing costs.

ASSET-InterTech highlighted its HSIO Validation Assistant, a new datamining tool for the company’s InterTech’s ScanWorks platform that automatically analyzes a database of signal-integrity test data. And ASSET and Cadence Design Systems demonstrated the interoperability of their IEEE 1687 Internal JTAG (IJTAG) tools, which enable the reuse of embedded IP both internally on chips and externally onto system boards.

Boundary-scan firms Goepel electronic, JTAG Technologies, and XJTAG also were on hand to highlight products based on the IEEE 1149.1 standard and its derivatives. In addition, Keysight Technologies exhibited its boundary scan analyzer.

Although not an exhibitor, Cadence was an ITC sponsor and had a team on hand addressing such topics as 3D TSV reliability and automated pattern retargeting in support of IEEE 1687. And Galaxy took advantage of the ITC corporate forum presentation area to describe its Examinator and Examinator Pro characterization tools, Yield-Man automated yield management tool, and PAT-Man DPM reduction tool.

SL Power Electronics exhibited its line of highly efficient power supply solutions for test-and-measurement applications. SL Power executives presented the company’s specifically designed power solutions for electronic, analytical, and communications test equipment applications. Products on display included the new TE Series 60-W external power supply and the new TB65 internal power supply.

In addition, Chroma Systems Solutions highlighted a mini tabletop test handler and source-measure units.

And finally, Applicos showcased the latest updates to its ATX7006 analog ATE, which the company describes as a highly accurate, compact device characterization system that is completely integrated for coherent mixed-signal measurements.

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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