Astronics at ITC touts expansion of SLT platform for IC test

Oct. 30, 2017

Fort Worth, TX. Astronics Test Systems today introduced an expansion of the ATS 5034 system-level-test (SLT) platform. Featuring new semi-automatic solutions in a scalable system, the ATS 5034 now offers lower volume, higher mix, small lot, and/or longer test-duration options for semiconductor manufacturers, the company reports.

With this introduction, the company said it now delivers configurations that facilitate the industry’s fastest, easiest development path from single-site to massively parallel system-level-test for semiconductor packages of all types.

“Customers continue to embrace System-Level Test, particularly where quality and yield are critical,” said Jon Sinskie, executive vice president of Astronics Test Systems, in a press release. “This platform expansion makes it easier for our customers to get started with SLT and scale as needed for their specific test plans and production ramps.”

Astronics said it has tested over 9 billion devices on more than 1,000 testers worldwide to support high-volume device production where massively parallel solutions are most economical. Now, the company said, it is bringing SLT to a broader market, making it achievable and affordable for customers to conduct true system performance testing on more semiconductors for a variety of mission-critical applications such as automotive, mobile, data, desktop, biomedical, and IoT devices.

For customers using this system, the workflow scales from a single-site to massively parallel test solution. It begins with a single-site device development board (DDB) kit, which in turn scales into a single-slot tester (SST). Next, Astronics can leverage the single-slot design into the multislot chamber (MSC), which sets the foundation for testing in massive parallelism. The MSC configuration also serves as a manual standalone low-volume solution until more production capacity is necessary. When needed, the MSC solution becomes semi-automatic with the addition of a semi-automatic board loader/unloader (BLU). To become fully automatic, the company integrates a high-speed handler to provide a turnkey SLT solution that can deliver testing at volume.

The versatility in this expandable platform approach supports the fastest development path to massively parallel test for commercializing emerging semiconductor-based products, the company said. Economically, the ATS 5034 SLT Platform enables the consolidation of many testers into one, where users can experience a reduction in cost of test, cost of ownership, and operating expenses (OPEX) for improved operational efficiency.

The ATS 5034 SLT platform can test up to 5,000 units per hour (UPH) and up to x396 sites in parallel for the fully-automatic configuration. It features easy-to-operate automation and lot management with ActivATE software. It also offers simple JEDEC-trays-in and JEDEC-trays-out operation and supports all popular package types, including system on chip (SoC), module, and heterogeneous system in package (SiP), with future supportability for new package types.

The company is highlighting the system at the International Test Conference in Fort Worth through November 2. ITC will also feature a “hot-topic virtual panel” titled “What does the test community really think about system-level test?” After ITC, on November 29 at 1 p.m. EST, Anil Bhalla and Karthik Ranganathan of Astronics will present a webcast titled “Key Trends Driving the Need for More Semiconductor System-Level Test.” I will serve as moderator. You can register here.

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