Imec Cadence 3 Nm

imec, Cadence tape-out industry’s first 3-nm test chip

March 1, 2018

Leuven, Belgium, and San Jose, CA. imec and Cadence Design Systems have announced that their extensive, long-standing collaboration has resulted in the industry’s first 3-nm test chip tapeout. The tapeout project, geared toward advancing 3-nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus implementation system and Genus synthesis solution. imec utilized a common industry 64-bit CPU for the test chip with a custom 3-nm standard-cell library and a TRIM metal flow, where the routing pitch was reduced to 21 nm. Together, Cadence and imec have enabled the 3-nm implementation flow to be fully validated in preparation for next-generation design innovation.

Post place-and-route layout of 21-nm-pitch metal layers

The Cadence Innovus implementation system is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance, and area (PPA) targets while accelerating time to market. The Cadence Genus synthesis solution is a next-generation, high-capacity RTL-synthesis and physical-synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10x.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.

“As process dimensions reduce to the 3-nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3-nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3-nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3-nm rule set.”

“imec’s state-of-the-art infrastructure enables preproduction innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “Expanding upon the work we did with imec in 2015 on the industry’s first 5-nm tapeout, we are achieving new milestones together with this new 3-nm tapeout, which can transform the future of mobile designs at advanced nodes.”

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