Tool Lends Concurrency To FPGA/PC-Board Design Process

Aug. 23, 2004
With many more faster and denser FPGAs finding their way onto pc boards, it's about time for FPGA and pc-board tools to begin to talk. If there's any hope of dealing with the complexities of pin assignments within the compressed timeframes of today's...

With many more faster and denser FPGAs finding their way onto pc boards, it's about time for FPGA and pc-board tools to begin to talk. If there's any hope of dealing with the complexities of pin assignments within the compressed timeframes of today's design cycles, designers need far better communication between the FPGA and pc-board flows.

Mentor's I/O Designer accomplishes just that, sitting between these flows and establishing bidirectional communication throughout the parallel processes of FPGA and pc-board design. Its early HDL descriptions of the FPGA provide automatic generation of schematic symbols to represent the FPGA in the pc-board design process. Then, it incrementally and bidirectionally manages FPGA pin assignments.

FPGAs have very specific rules that must be followed regarding which pins may be used for particular purposes. In I/O Designer, signals are graphically assigned to designated pins in a guided FPGA library environment. An easy-to-use, drag-and-drop GUI lets either FPGA or pc-board designers assign pinouts. The tool comes with device libraries for three major FPGA vendors, giving it access to all applicable design rules and ensuring correct designs.

Attempting to assign pinouts and perform pc-board routing without communicating pinout constraints to the pc-board tools can result in routing and timing nightmares. That's because a pc-board router will match wire lengths to meet timing using the lowest common denominator, i.e., the longest net, as its basis.

To solve these issues, I/O Designer communicates all allowable FPGA pin-swaps to the pc-board design environment and synchronizes pinout assignments between the FPGA and pc-board design environments for rapid timing closure and routing completion. Users can intelligently assign signals to pins on the FPGA while considering the rules of the device's architecture.

I/O Designer is available now. Prices start at $10,000. It integrates Mentor's Board Station, Expedition, and PADS pc-board tools with its FPGA Advantage integrated FPGA design flow as well as with design tools from major FPGA vendors.

Mentor Graphicswww.mentor.com/expedition/io_designer.html
About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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