Interconnect Technology Boosts Chip Communication Rates

April 16, 2001
A novel point-to-point bus technology known as HyperTransport brings greater bandwidth to a range of applications, including servers, workstations, network switches, and embedded applications. Developed by Advanced Micro Devices of Sunnyvale,...

A novel point-to-point bus technology known as HyperTransport brings greater bandwidth to a range of applications, including servers, workstations, network switches, and embedded applications. Developed by Advanced Micro Devices of Sunnyvale, Calif., it eliminates I/O bottlenecks. This enables chips inside of PCs and networking devices to communicate with each other up to 50 times faster than existing data-transfer rates.

Interconnecting ICs on a motherboard, the technology achieves greater speeds than a PCI bus for an equivalent number of pins—50 times faster than PCI, six times faster than PCI-X, and five times faster than InfiniBand's four-channel implementation. The maximum possible configuration is 1.6 Gtransfers/s.

Each HyperTransport I/O bus consists of two point-to-point unidirectional links. These links may be from two to 32 bits wide. They support the 2-, 4-, 8-, 16-, and 32-bit standard bus widths. Engineers can design the link in each direction, specifying the width of the bus and the clock rate of the system. Commands, addresses, and data (CAD) all use the same bits. For example, a simple HyperTransport I/O implementation using two CAD bits in each direction provides a raw bandwidth of up to 400 Mbytes/s in each direction.

Larger Version Also A larger HyperTransport implementation employing 16 CAD bits in each direction yields a bandwidth of up to 3.2 Gbytes/s in both directions. This rate is 48 times the peak bandwidth of a 32-bit PCI running at 33 MHz. It supports an aggregate bandwidth of 6.4 Gbytes/s with a maximum transfer rate of 1.6 Gbits/s using the 16-bit wide implementation in both directions. The company projects that most users will use the 800-Mtransfer/s and 1.6-Gtransfer/s rates.

The technology lets developers design components that interoperate with various processor platforms. It also acts as a building block for enterprise-level server solutions based on AMD's next-generation family of processors. Primarily targeted at IT and telecom industries, HyperTransport can be optimized for any application where high speed, low latency, and scalability are required. Designed to be transparent to operating systems, it's also extensible to systems network architecture (SNA) buses.

AMD has signed agreements with various partners throughout the IT and communications industries to produce devices based upon HyperTransport technology. The first volume products from AMD to support this technology should debut in 2002. For more information, visit www.amd.com.

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