32-Mbit SRAM Stack Saves Board Space

Dec. 1, 1998
Based on JEDEC standard 84-pin PLCC SRAM chips, the PUMA 84S32000 is a 32-bit CMOS, high-speed memory stack with access times of 20, 25 and 35 ns over commercial and industrial temperature ranges. The memory stacking technology used here provides

Based on JEDEC standard 84-pin PLCC SRAM chips, the PUMA 84S32000 is a 32-bit CMOS, high-speed memory stack with access times of 20, 25 and 35 ns over commercial and industrial temperature ranges. The memory stacking technology used here provides ultra high density devices and can accommodate EEPROM, SRAM, Flash, or mixed memory ICs.With dimensions of only 30.35 x 30.35 x 8.5 mm max., the SRAM stack can be user configured as 1M x 32, 2M x 16, or 4M x 8 organized memories. The device, which is screened to ensure its reliability, features multiple ground pins for high noise immunity and TTL compatible inputs and outputs. Operating power in 32-bit mode is 7.04W max. and standby power is 440 mW.

Company: MOSAIC SEMICONDUCTOR INC.

Product URL: Click here for more information

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