Communications: Digital Downconverter Handles 64 Channels, Delivers 140 Msamples/s

Feb. 16, 2006

A fully flexible 64-channel digital downconversion (DDC) core is tuned for use on FPGAs. The ChannelCore64 lets designers replace up to 16 specialized DDC ASIC devices with a single IP core, significantly reducing board area, lowering power consumption, and increasing flexibility. The ChannelCore64 can considerably reduce system cost compared to traditional methods, with savings becoming more significant as the number of channels increases. The DDC core targets applications such as wireless basestations, satellite ground stations, and other multichannel radio receivers. The core supports two 16-bit analog-to-digital converter (ADC) inputs, each with a sample rate up to 140 Msamples/s. It also provides 64 independent downconversion channels, which may be connected to either ADC. Designers can independently tune channel center frequencies with a resolution of less than 0.01 Hz and independently select channel bandwidths. Channels can be reconfigured while the core is running without affecting the operation of other channels. Contact the company for licensing fees.

RF Engines Ltd.
www.rfel.com

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.