AMD Hammers Multiprocessor Hyperchannel
Multiprocessor system design will get a little easier with AMD's new 64-bit "Hammer" processors that utilize multiple Hyperchannel links to access shared memory and peripherals. The key to the system is a crossbar switch found in the core of each Hammer processor. The switch routes local-memory requests to the on-board DDR memory controller and forwards nonlocal requests to other processors over Hyperchannel links.
AMD has coined the term SUMO (sufficiently uniform memory organization) for its approach to memory access. The architecture is very similar to nonuniform memory architecture (NUMA) systems that have a wide range of asymmetrical access times.
But with SUMO, latency difference between local and nonlocal memory is comparable to the difference be-tween a page hit and a page conflict. Caching and bulk memory transfers help minimize these effects. AMD also eliminates the North bridge while improving memory scalability since every processor has its own memory controller.
The crossbar switch and Hyperchannel links are slightly more complex than might first be assumed. For example, the system must take into account caches on each processor. So, memory accesses actually invoke cache-coherence message traffic across the links.
The architecture scales to eight processors. HyperTransport scales from one to three links and 2- to 32-bit full-duplex connections. Aggregate bandwidth can reach 19.2 Gbytes/s.
SUMO makes system building blocks easier to work with and removes I/O bottlenecks found in many SMP architectures.
The unified memory and peripheral architecture also simplifies processor design and peripheral interface design. Peripheral interfaces can be created using I/O hubs. High-speed interfaces can be implemented using HyperTransport bridges to technologies such as InfiniBand or Gigabit Ethernet. Overall, it's a very elegant design. www.amd.com
PSoC Designer Morphs Microcontroller
Reconfigurable microcontrollers can be difficult to program without using a handy tool like Cypress Semiconductor's PSoC Designer. Of course, it also helps to have an 8-bit microcontroller chip, such as the Cypress CY8C25x/26x. The pair mesh nicely. The design software uses a drag-and-drop interface for configuring the digital and analog blocks, and it generates the C and assembler header files for the configured hardware.
The task of laying out a programmable hardware design isn't difficult, but it becomes more challenging when the chip can morph from one configuration to another at runtime. PSoC Designer can generate multiple configurations for just this type of environment. Each configuration is independent, although it's possible to selectively reconfigure only part of the chip.
All aspects of the system can be reconfigured, keeping in mind the interconnection architecture of the chip. There are common bus lines that can connect internal devices together, or to external pins. Interrupts can be configured in a similar fashion. The design software incorporates a simulator with a full trace mode. www.cypress.com
16-Bit Micro Cuts Power Consumption
Cyan Technology's eCOG1 16-bit microcontroller architecture keeps power requirements low, while servicing multiple communication links. The key to keeping power consumption down is independent clocking of the processor and peripherals, along with intelligent peripheral support. This allows the processor to be slowed or stopped while data is sent or received. The processor is sped up when interrupts occur.
The chip operates from a low-cost, 25-MHz watch crystal. Other clock frequencies are generated from this, allowing each on-board device to operate at its optimum frequency. The intelligent communications supports a pair of serial links that can operate as USARTs, SPI, IR, IrDA, I2C, or a SmartCard interface. There also is a pair of UARTs. All of this is managed by a state machine that has access to 4 kbytes of RAM.
Amino Communications' high-speed IntAct serial link provides a secure interface between multiple microcontrollers. The link consists of two full-duplex 2-bit wide channels with an aggregate throughput of 720 Mbits/s.
The eCOG1 includes the usual complement of standard peripherals like a GPIO, timers, a four-channel 12-bit ADC, and PWM outputs. Other on-board peripherals reduce external parts count, including brownout and temperature sensors, plus power-on reset. An integrated ICE takes advantage of cache integration, so breakpoints can be set and locked into the processor's cache in real time. www.cyantechnology.com
