Intelligent Retiming Chip Provides Four 3.125-Gbit/s Full-Duplex Channels

June 10, 2002

The nPower BBT3401 intelligent retiming chip's four full-duplex channels can each operate at data rates from 800 Mbits/s to 3.125 Gbits/s. The highly integrated chip can replace as many as six lower-integration chips. Consuming just 200 mW per channel, it's one of the lowest-power retiming solutions available, reducing power consumption by almost 50% over other products. Each channel can restore data streams to their original state by synchronizing, deskewing across all four channels, and reducing jitter.

Recovered data can be sent at rates of 800 Mbits/s up to 3.125 Gbits/s across a backplane of up to 40 in. on FR-4 pc-board material. The BT3401 can synchronize incoming data to a system's local clock by removing (or inserting) IDLE bits embedded between data packets. A two-pin interface provides access to the internal MDIP/MDC control registers. The control registers activate a bypass circuit that lets the data stream bypass the 8B/10B encoders/decoders so designers can implement custom coding schemes. Another command loops the transmitter of each channel back to its receiver, letting the chip test itself.

In lots of 1000, the BBT3401 costs $47 housed in a 144-contact low-profile BGA package.

BitBlitz Communications
www.bitblitz.com; (510) 656-4600

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.