Single-Chip Digital Set-Top Box Controller Enables 225 MIPS

The STB034xx integrates IBM's PowerPC 405 processor with subsystems from IBM's family of set-top box functions—all on one chip. By allowing the base audio and decoding activities to execute with minimal host processing, this set-top box...
June 12, 2000
3 min read

The STB034xx integrates IBM's PowerPC 405 processor with subsystems from IBM's family of set-top box functions—all on one chip. By allowing the base audio and decoding activities to execute with minimal host processing, this set-top box controller can perform 225 MIPS. Its integrated drive electronics interface and antiflicker filter enhance digital video-recording and web-browsing applications.

The controller brings significant benefits in system performance to set-top box designers, who can use it to transform a TV into a fully interactive two-way information appliance. Made in 0.25-µm CMOS, the device comprises four subsystems: a processor, a memory interface, digital/audio/video, and peripherals.

The PowerPC 405 processor, the heart of its respective subsystem, boasts high-speed operation at 162 MHz. It has 16 kbytes of instruction cache and 8 kbytes of data cache. Meanwhile, the memory subsystem includes two SDRAM interfaces with up to 16 Mbytes each, a four-channel DMA circuit, an IDE interface, and up to 128 Mbytes of SRAM, ROM, or flash memory.

The digital/audio/video subsystem delivers high-quality video and sound. It lets service providers offer graphically rich user interfaces for next-generation interactive applications. An MPEG-2 video decoder comes with an antiflicker filter. Five on-screen display/video planes decode MPEG-2 Main Profile at Main Level (MP @ ML) video. Additionally, the subsystem has an MPEG-2 transport and a DVB descrambler.

MPEG-2 layer I and layer II (CD-quality) audio is decoded by an MPEG-2 audio decoder. This subsystem also has a digital encoder, including NTSC/PAL analog conversion and six concurrent analog video outputs. It's compatible with SCAR connectors and audio phase-locked loops, too. Options available include Macrovision copy protection support and Dolby digital audio support as an alternative to MPEG-2 layer 1 and layer 2 audio.

The peripherals subsystem provides a range of interfaces that designers need to meet customers' requirements. General-purpose timers, pulse-width modulation, an IEEE 1284 peripheral interface, and two smart-card interfaces are all packed into the subsystem. So are two I2C interfaces, a UART interface (16550), and serial and infrared communications controllers. These interfaces also include a serial control port, a modem I/F, and general-purpose input/output controllers.

Evaluation kits are available to help improve manufacturers' time-to-market needs. These kits feature source code and a circuit board. And, they have development tools hosted by Windows 98, such as a C/C++ compiler and RISCWatch debugger, for noninvasive RTOS-aware debug.

The controller itself requires 2.5- and 3.3-V supply voltages, and its power dissipation is approximately 2.5 W.

The STB034xx is shipped in a 304-pin, 31-mm plastic BGA package. Samples are available now. Production volumes are slated for July. A 108-MHz, 150-MIPS version of the device will be available in the second half of the year.

IBM North American Sales Office Headquarters, IBM Microelectronics Division, 281 Winter St., Waltham, MA 02451; (781) 642-5900; fax (781) 788-0978; www.chips.ibm.com.

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