MOSFET Package Packs More Die, Less On-Resistance

A power-MOSFET package developed by Intersil Corp. of Irvine, Calif., boosts device efficiency by lowering package resistance and making room for larger die. Known as the MicroFET, this wire-bonded package increases efficiency in space-conscious power designs, particularly in battery-operated portable products. These applications also will benefit from the MicroFET's reduced package height.

Initially, the MicroFET will be offered in an SO-8-compatible footprint. Other industry-standard footprints will follow. Compared to a standard SO-8, the MicroFET has two distinguishing characteristics—integral leads and an exposed die-attach pad (see the figure).

The MicroFET's leads are integrated within the package, so they're shorter than an SO-8's leads. As a result, packaging resistance is 50% lower. The leads also provide space for a larger die-attach paddle. The paddle lets the MicroFET hold a die that's over twice the size of a die intended for the SO-8. This reduces the MOSFET R_DS(ON) even further.

The exposed die-attach pad solders directly to the pc board, significantly enhancing thermal performance. Thermal resistance junction-to-case is typically 60°C/W, versus 30°C/W for the SO-8. Additionally, the MicroFET's package is half as tall as the SO-8.

The MicroFET will be used to enhance the performance of the company's DenseTrench MOSFETs and UltraFET products, which are built in a striped planar process. MicroFET products in the SO-8 footprint are scheduled for release in the fourth quarter of this year.

To promote acceptance of the MicroFET as an industry standard, Intersil is working with different packaging manufacturers to allow open tooling of the package design. For more information, see www.intersil.com/mosfets/microfet, or contact Krishna Kuchimanchi at (321) 729-4148.