Receiver Drives Base Stations To EDGE

The EDGE standard is quickly becoming a key linchpin in the migration to 3G. Many factors support this statement. For starters, today's operators want and need to drive up revenue. With the high-speed data rates that it enables, EDGE is seen as one way for them to accomplish this goal. By the very nature of the modulation scheme that it employs—8 PSK as opposed to GMSK—EDGE offers a 3X increase in speed. Of course, this standard does require some initial hardware implementation. Once the hardware has been taken care of, however, it just takes a simple software upgrade to get EDGE up and running.

Operators have spent billions on UMTS frequency spectrum. However, in the interim, EDGE is becoming an important stepping stone to provide consumers with high-speed data as an extension of existing GSM networks. Thus, more operators are now struggling to get EDGE solutions to work as quickly as possible. There is just one catch: EDGE is challenging. It uses the same frequency bands, channel bandwidth, and network protocol as GSM/GPRS. But enabling it to work properly requires higher-performance analog, RF, and DSP components.

One vendor understands these needs so well that it came up with a viable EDGE-based solution. That vendor is Analog Devices, Inc. (ADI). Its solution is an integrated IF-to-baseband diversity GSM/EDGE receiver for wireless base stations (FIG. 1). Known as the AD6650, this device effectively integrates the functionality of seven components into a single chip. At the same time, it allows base-station designers to meet strict EDGE performance requirements. Best of all, it grants a possible 50% reduction in cost over existing solutions offering the same functionality.

The AD6650 diversity receiver is a member of the mixed-signal front-end (MxFE) family of products. Each family member is based on ADI's smart-partitioning technology, which leverages the company's high-performance data-converter and radio capabilities. This technology partitions the signal path according to performance-enhancing, rather than analog/digital, boundaries. In the case of the AD6650, an example of this partitioning is the combination of the analog and digital filters. The analog filter is utilized as an anti-aliasing filter for the ADCs, while the programmable digital filter provides precise channel selectivity. As a result, the AD6650 effectively eliminates the need for five active components and two SAW filters from today's existing solutions.

The AD6650 chip requires only one external SAW filter for the entire receive (Rx) signal path to meet GSM/EDGE blocking requirements. Note that one SAW filter is required for main and one is required for diversity. As the component count drops, so too does board size and test cost. System cost also is reduced, thanks to optimized baseband-signal processing.

Chris Cloninger, Analog Devices' Systems Application Engineer for Digital Radio Systems, describes the new product this way: "The AD6650 receiver offers the highest dynamic range at high analog-input frequencies in a single, low-cost IC (FIG. 2). This performance leverages Analog Devices' leading technology, which includes high-speed converters, quadrature demodulation, active filters, PLL, VCO, and digital signal processing."

The AD6650 chip, with its 1.2-W, 3.3-V I/O operation and CMOS core, can accommodate IF input frequencies from 70 to 300 MHz. It flaunts an impressive 10-dB noise figure with 24-dBm input IP2 and −13-dBm input IP3 (FIG. 3). The receiver also houses low-phase-noise PLL circuitry with an integrated VCO. This circuitry is characterized by 125 dBc at around 800 kHz. Among the receiver's other features are serial-data output ports, an I²C, and a microprocessor interface. The serial outputs to the DSP have the net effect of reducing pin count. The device also boasts JTAG boundary scan for simplified testing.

This narrowband, single-chip diversity receiver comes fully integrated with a digitally controlled variable-gain amplifier (VGA). This amplifier acts as part of an on-board, automatic-gain-control loop and an IF-to-baseband I&Q demodulator. Active analog low-pass filtering and multiplexed, dual-wideband analog-to-digital converters are included as well. The task of driving the I&Q demodulator falls to the on-chip synthesizer with an integrated VCO.

In addition, the AD6650 device houses integrated digital decimation and channel filters (52-MSample/s or 104-MSample/s master clock). They work to generate serial-output I&Q data streams. These filters also remove unwanted signals and noise outside the channel of interest. Programmable-RAM coefficient filters permit anti-aliasing, matched-filtering, and static-equalization functions to be combined in a single, cost-effective filter.

As seen in recent studies, GSM/EDGE will most likely remain a volume market for a number of years. By some estimates, that timeframe may extend to 2008 and beyond. It's therefore critical to find ways to address the performance and cost needs of single-carrier solutions. This must be done successfully before the industry's jump to multi-carrier solutions. ADI's AD6650 can effectively address the issues of cost and performance, thanks to the host of innovative techniques employed by its designers.

Because the designers reduced the device's component count, for instance, the receive chain becomes very compact. The result is a size and cost reduction. ADI estimates that the board-area savings alone can be somewhere in the neighborhood of 40%. Coupled with a 50% cost savings over existing solutions, these features make the AD6650 even more viable for GSM/EDGE base stations.

The elimination of two SAW filters highlights another key benefit: the 115-dB total dynamic range. Simply put, more dynamic range is required. The receiver needs it in order to absorb the performance that is no longer handled by the eliminated SAW filters.

The AD6650 also boasts back-end DC correction and a digital AGC loop. In typical baseband architectures, there is DC offset, which is primarily associated with the ADCs. The AD6650 actively monitors and removes this offset. It also uses a digital AGC loop to monitor the input. This loop helps maintain the maximum signal-to-noise ratio (SNR) throughout the device. Both of these functions are software programmable and serve to guarantee that the strict sensitivity specifications for EDGE are met.

The integration flaunted by the AD6650 also is unique. Such a high level of integration is very unusual for a device with a specified 115-dB dynamic range. The device also stands out because it has an inductor integrated on chip. In the case of the AD6650, this step was needed to reduce cost. An external VCO alone can cost upwards of $5 to $10.

The AD6650 IF-to-baseband diversity receiver is now sampling. Full production is scheduled to begin in the fall of 2003. It comes in a 121-pin, plastic ball-grid-array (BGA) package. In 1000-piece quantities, the receiver has a starting price of $20.00 per unit.