ADSL Front End Cuts Chip Count And Power

Helping pave the way for increasing DSL line card densities from four to eight to 16, 24 or 32 channels, this two-chip analog front end (AFE) promises to reduce chip counts on pc boards while also reducing power consumption by 20% compared to previous solutions. The front end consists of the TLV320AD15 eight-channel codec with 14-bit converters and a separate driver and receiver device, which can take the form of the THS7102 for DSL over POTS applications or the THS7103 for delivering DSL over ISDN lines. Each of the codec’s channels can be powered down separately, with the chip also featuring separate serial interfaces for each channel: one for codec transfer, the other for transfer-control information.
The driver/receiver chips include a low-differential receiver, a low power active termination differential line driver, integrated transmit filters, and integrated transmit and receive resistors. Both devices, as well as the codec, support G.lite and full-rate discrete multi-tone (DMT) ADSL communications. And all three chips contribute to the new front-end’s lower power consumption, with the TLV320AD15 codec operating from either a 3.3V supply or 3.3V and 1.5V supplies, while the driver/receiver devices can operate off of a single 15V supply—power consumption for the driver/receiver devices is just 1.1W/channel versus 1.5W/channel for existing devices. And with an operating temperature range of -40°C to 85°C, the front-end chips can be used in DLC systems deployed in cabinets to be installed in the field.
The TLV320AD15 codec comes in 240-ball BGA costing $52 each/100K, while the THS7102 and THS7103 come in 80-ball BGAs or 32-pin PQFPs priced at $5.59 each.