Pseudo SRAM Ups Density And Lowers Cost

Sept. 1, 2001
A new 32-Mb Pseudo-SRAM device is said to offer twice the density of traditional SRAM solutions, while significantly reducing the cost per bit for emerging wireless devices. The Pseudo-SRAM's standard SRAM interface and 1-transistor DRAM-like memory

A new 32-Mb Pseudo-SRAM device is said to offer twice the density of traditional SRAM solutions, while significantly reducing the cost per bit for emerging wireless devices. The Pseudo-SRAM's standard SRAM interface and 1-transistor DRAM-like memory cell make it an easy design-in for cellular phone and PDA applications, according to the company. And unlike standard DRAM solutions, the 32Mb Pseudo-SRAM does not require a separate DRAM controller, thus enabling smaller packaging and saving board space. Glue-logic, which is typically needed for the refresh operations with standard DRAM is not required for Pseudo-SRAM. It operates using a single power supply with a voltage range of 2.5V to 3.1V. Standby current is 70 (A with a deep power down standby mode of 5 (A. The device operates in a page mode with a page read operation of four words and is logic compatible with SRAM write enable input. Technical specifications include a 2Mb x 16 configuration and 80 ns access time. Designated TC51W3216XB, the device comes in a 48-ball FBGA package and is priced at $26 each in sample quantities. TOSHIBA AMERICA ELECTRONIC COMPONENTS INC. (TAEC). Irvine, CA. (949) 455-2000

Company: TOSHIBA AMERICA ELECTRONIC COMPONENTS INC. (TAEC)

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