Tabula Stylus design flow
Tabula Stylus cloud configuration
Tabula Stylus IDE via VNC
Tabula ABAX development board
Tabula's ABAX FPGA implements a unique 3D SpaceTime architecture (see FPGAs Enter The Third Dimension) This time-based system implements an FPGA in logical layers that are activated in sequence. This essentially multiplies the amount of hardware by the number of layers used by the design.
The latest announcement is the release of Tabula's Stylus development platform. It provides a conventional FPGA design flow (Fig. 1) The difference has little to do with the SpaceTime architecture that is effectively transparent to the designer. Instead, the notable feature of the tool is that it is web-based (Fig. 2).
I had a chance to check out Stylus (Fig. 3). It actually runs on a Linux platform on Tabula's development site and is accessed using VNC (Virtual Computing Network). VNC is the typical remote control platform on a Linux system and works on most operating systems like Windows.
There are a number of advantages to this approach. First, start up costs are minimal. Second, there is really no set up necessary since VNC can even be used through a web browser. Third, tech support is always on hand and can share the console when helping out a developer. Finally, the software will always be up to date.
There are issues that can arise because the design files are located on the server. Uploading, downloading and backups can be an issue. Customers have access to their files. A high speed Internet connection is a requirement but not a problem given the general availability of this type of support. Security for this type of configuration may be an issue for some customers but so far Tabula has found quite a few that like the set up.
Stylus deals with RTL, VHDL, Verilog and System Verilog. It provides a place and route compiler that targets the ABAX FPGAs. The result can be examined with respect to the SpaceTime support. This is more for information since the ABAX FPGA acts like a conventional FPGA from an execution perspective.
The actual control of the SpaceTime layering is controlled by timing constraints that are normally part of the system design. These constraints can be adjusted to change the resulting configuration but I found that simply ignoring the SpaceTime layered architecture was easy.
The resulting project can be downloaded to a platform like Tabula's $7500 ABAX development board (Fig. 4). I did not have one handy so I could only enjoy the resulting analysis files showing the SpaceTime layout. Ths board shows off ABAX features like PCI-Express Gen1/Gen2, Ethernet 10/100/1000/10000, DDR3 support and even V1 ColdFire support.
Developers familiar with almost any FPGA development tool will be at ease using Stylus. Stylus is complete so it is possible to build a design from the base up in addition to being able to bring an existing design into Stylus.
One thing I didn't get to try out is the on-chip debug support. This obviously requires a chip to try it out on. I have heard it is on par with similar facilities found in Xilinx and Altera development platforms.